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PDF CY7C1446AV25 Data sheet ( Hoja de datos )
| Número de pieza | CY7C1446AV25 | |
| Descripción | 36-Mbit Pipelined Sync SRAM | |
| Fabricantes | Cypress Semiconductor | |
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CY7C1440AV25
CY7C1446AV25
36-Mbit (1 M × 36/512 K × 72)
Pipelined Sync SRAM
36-Mbit (1 M × 36/512 K × 72) Pipelined Sync SRAM
Features
■ Supports bus operation up to 250 MHz
■ Available speed grades are 250 and 167 MHz
■ Registered inputs and outputs for pipelined operation
■ 2.5 V core power supply
■ 2.5 V power supply
■ Fast clock-to-output times
❐ 2.6 ns (for 250-MHz device)
■ Provide high-performance 3-1-1-1 access rate
■ User-selectable burst counter supporting Intel Pentium
interleaved or linear burst sequences
■ Separate processor and controller address strobes
■ Synchronous self-timed writes
■ Asynchronous output enable
■ Single-cycle Chip Deselect
■ CY7C1440AV25 available in Pb-free and non-Pb-free 165-ball
FBGA package. CY7C1446AV25 available in non-Pb-free
209-ball FBGA package
■ IEEE 1149.1 JTAG-Compatible Boundary Scan
■ “ZZ” Sleep Mode Option
Functional Description
The CY7C1440AV25/CY7C1446AV25 SRAM integrates
1 M × 36/512 K × 72 SRAM cells with advanced synchronous
peripheral circuitry and a two-bit counter for internal burst
operation. All synchronous inputs are gated by registers
controlled by a positive-edge-triggered Clock Input (CLK). The
synchronous inputs include all addresses, all data inputs,
address-pipelining Chip Enable (CE1), depth-expansion Chip
Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and
ADV), Write Enables (BWX, and BWE), and Global Write (GW).
Asynchronous inputs include the Output Enable (OE) and the ZZ
pin.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or Address
Strobe Controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to two or four bytes wide as
controlled by the byte write control inputs. GW when active LOW
causes all bytes to be written.
The CY7C1440AV25/CY7C1446AV25 operates from a +2.5 V
core power supply while all outputs may operate with a +2.5 V
supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
For a complete list of related documentation, click here.
Selection Guide
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Description
250 MHz
2.6
435
120
167 MHz
3.4
335
120
Unit
ns
mA
mA
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-70167 Rev. *E
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 5, 2016
1 page  
CY7C1440AV25
CY7C1446AV25
Pin Configurations
Figure 1. 165-ball FBGA (15 × 17 × 1.4 mm) pinout
CY7C1440AV25 (1 M × 36)
123
A NC/288M
B NC/144M
A
A
CE1
CE2
C DQPC NC VDDQ
D
DQC
DQC
VDDQ
E
DQC
DQC
VDDQ
F
DQC
DQC
VDDQ
G
DQC
DQC
VDDQ
H NC NC NC
J
DQD
DQD
VDDQ
K
DQD
DQD
VDDQ
L
DQD
DQD
VDDQ
M
DQD
DQD
VDDQ
N DQPD NC VDDQ
P NC NC/72M A
R MODE
A
A
4
BWC
BWD
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A
A
5
BWB
BWA
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
TDI
TMS
6
CE3
CLK
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
A1
A0
7
BWE
GW
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
TDO
TCK
8
ADSC
OE
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A
A
9
ADV
ADSP
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
A
10 11
A NC
A NC/576M
NC/1G
DQB
DQB
DQB
DQB
NC
DQPB
DQB
DQB
DQB
DQB
ZZ
DQA
DQA
DQA
DQA
NC
A
DQA
DQA
DQA
DQA
DQPA
A
AA
Document Number: 001-70167 Rev. *E
Page 5 of 33
5 Page 
CY7C1440AV25
CY7C1446AV25
Truth Table for Read/Write
The Truth Table for Read/Write for CY7C1440AV25 follows. [7, 8, 9]
Function (CY7C1440AV25)
Read
Read
Write Byte A – (DQA and DQPA)
Write Byte B – (DQB and DQPB)
Write Bytes B, A
Write Byte C – (DQC and DQPC)
Write Bytes C, A
Write Bytes C, B
Write Bytes C, B, A
Write Byte D – (DQD and DQPD)
Write Bytes D, A
Write Bytes D, B
Write Bytes D, B, A
Write Bytes D, C
Write Bytes D, C, A
Write Bytes D, C, B
Write All Bytes
Write All Bytes
GW
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
BWE
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
BWD
X
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
X
BWC
X
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
X
BWB
X
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
X
BWA
X
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
X
Truth Table for Read/Write
The Truth Table for Read/Write for CY7C1446AV25 follows. [7, 8, 9]
Function (CY7C1446AV25)
Read
Read
Write Byte x – (DQx and DQPx)
Write All Bytes
GW
H
H
H
H
BWE
H
L
L
L
BWx
X
All BW = H
L
All BW = L
Notes
7. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
8.
BWx represents any
at the same time for
byte write
any given
signal.
write.
To
enable
any
byte
write
BWx,
a
Logic
LOW
signal
should
be
applied
at
clock
rise.
Any
number
of
bye
writes
can
be
enabled
9. Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write will be done based on which byte write is active.
Document Number: 001-70167 Rev. *E
Page 11 of 33
11 Page | ||
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