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PDF CY7C1441AV33 Data sheet ( Hoja de datos )
| Número de pieza | CY7C1441AV33 | |
| Descripción | 36-Mbit Flow-Through SRAM | |
| Fabricantes | Cypress Semiconductor | |
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CY7C1441AV33
36-Mbit (1 M × 36) Flow-Through SRAM
36-Mbit (1 M × 36) Flow-Through SRAM
Features
■ Supports 133-MHz bus operations
■ 1 M × 36 common I/O
■ 3.3 V core power supply
■ 2.5 V or 3.3 V I/O power supply
■ Fast clock-to-output times
❐ 6.5 ns (133-MHz version)
■ Provide high-performance 2-1-1-1 access rate
■ User-selectable burst counter supporting Intel Pentium
interleaved or linear burst sequences
■ Separate processor and controller address strobes
■ Synchronous self-timed write
■ Asynchronous output enable
■ CY7C1441AV33 available in JEDEC-standard Pb-free 100-pin
TQFP package, Pb-free 165-ball FBGA package.
■ IEEE 1149.1 JTAG-Compatible Boundary Scan
■ “ZZ” Sleep Mode option
Selection Guide
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Description
Functional Description
The CY7C1441AV33 are 3.3 V, 1 M × 36 Synchronous
Flow-through SRAMs, respectively designed to interface with
high-speed microprocessors with minimum glue logic. Maximum
access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit
on-chip counter captures the first address in a burst and
increments the address automatically for the rest of the burst
access. All synchronous inputs are gated by registers controlled
by a positive-edge-triggered Clock Input (CLK). The
synchronous inputs include all addresses, all data inputs,
address-pipelining Chip Enable (CE1), depth-expansion Chip
Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and
ADV), Write Enables (BWx, and BWE), and Global Write (GW).
Asynchronous inputs include the Output Enable (OE) and the ZZ
pin.
The CY7C1441AV33 allows either interleaved or linear burst
sequences, selected by the MODE input pin. A HIGH selects an
interleaved burst sequence, while a LOW selects a linear burst
sequence. Burst accesses can be initiated with the Processor
Address Strobe (ADSP) or the cache Controller Address Strobe
(ADSC) inputs. Address advancement is controlled by the
Address Advancement (ADV) input.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or Address
Strobe Controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
Advance pin (ADV).
The CY7C1441AV33 operates from a +3.3 V core power supply
while all outputs may operate with either a +2.5 or +3.3 V supply.
All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
For a complete list of related documentation, click here.
133 MHz
6.5
310
120
Unit
ns
mA
mA
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05357 Rev. *M
• San Jose, CA 95134-1709 • 408-943-2600
Revised December 29, 2014
1 page  
CY7C1441AV33
Pin Configurations (continued)
Figure 2. 165-ball FBGA (15 × 17 × 1.4 mm) pinout
123
A NC/288M A
CE1
B NC/144M A
C DQPC NC
D
DQC
DQC
CE2
VDDQ
VDDQ
E
DQC
DQC
VDDQ
F
DQC
DQC
VDDQ
G
DQC
DQC
VDDQ
H NC NC NC
J
DQD
DQD
VDDQ
K
DQD
DQD
VDDQ
L
DQD
DQD
VDDQ
M
DQD
DQD
VDDQ
N DQPD NC VDDQ
P NC NC/72M A
R MODE
A
A
CY7C1441AV33 (1 M × 36)
4 567
BWC
BWB
CE3
BWE
BWD
VSS
VDD
BWA
VSS
VSS
CLK
VSS
VSS
GW
VSS
VSS
VDD
VSS
VSS
VSS
VDD
VSS
VSS
VSS
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VSS
VSS
VSS
VDD
VSS
VSS
VSS
VDD
VSS
VSS
VSS
VSS NC A NC
A TDI A1 TDO
A TMS A0 TCK
8
ADSC
OE
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A
A
9
ADV
ADSP
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
A
10 11
A NC
A NC/576M
NC/1G
DQB
DQB
DQB
DQB
NC
DQPB
DQB
DQB
DQB
DQB
ZZ
DQA
DQA
DQA
DQA
NC
A
DQA
DQA
DQA
DQA
DQPA
A
AA
Document Number: 38-05357 Rev. *M
Page 5 of 34
5 Page 
CY7C1441AV33
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1441AV33 incorporates a serial boundary scan test
access port (TAP). This part is fully compliant with 1149.1. The
TAP operates using JEDEC-standard 3.3 V or 2.5 V I/O logic
levels.
The CY7C1441AV33 contains a TAP controller, instruction
register, boundary scan register, bypass register, and ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may
alternately be connected to VDD through a pull up resistor. TDO
should be left unconnected. Upon power up, the device comes
up in a reset state which does not interfere with the operation of
the device.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to leave
this ball unconnected if the TAP is not used. The ball is pulled up
internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI ball is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. TDI is internally pulled
up and can be unconnected if the TAP is unused in an
application. TDI is connected to the most significant bit (MSB) of
any register.
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current state
of the TAP state machine. The output changes on the falling edge
of TCK. TDO is connected to the least significant bit (LSB) of any
register.
Performing a TAP Reset
A RESET is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of the
SRAM and may be performed while the SRAM is operating.
At power up, the TAP is reset internally to ensure that TDO
comes up in a High Z state.
TAP Registers
Registers are connected between the TDI and TDO balls and
scan data into and out of the SRAM test circuitry. Only one
register can be selected at a time through the instruction register.
Data is serially loaded into the TDI ball on the rising edge of TCK.
Data is output on the TDO ball on the falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO balls as shown in the TAP Controller Block Diagram on
page 14. Upon power up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as described
in the previous section.
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary “01” pattern to allow for
fault isolation of the board-level serial test data path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This shifts data through the SRAM with
minimal delay. The bypass register is set LOW (VSS) when the
BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM. The length of the boundary scan
register for the SRAM in different packages is listed in the Scan
Register Sizes on page 17.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR state
and is then placed between the TDI and TDO balls when the
controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used to
capture the contents of the I/O ring.
The Boundary Scan Order tables show the order in which the bits
are connected. Each bit corresponds to one of the bumps on the
SRAM package. The MSB of the register is connected to TDI,
and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in the Identification Register Definitions on
page 17.
TAP Instruction Set
Overview
Eight different instructions are possible with the three bit
instruction register. All combinations are listed in the
Identification Codes on page 17. Three of these instructions are
listed as RESERVED and should not be used. The other five
instructions are described in this section in detail.
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO balls. To execute
Document Number: 38-05357 Rev. *M
Page 11 of 34
11 Page | ||
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