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PDF CY7C1367C Data sheet ( Hoja de datos )
| Número de pieza | CY7C1367C | |
| Descripción | 9-Mbit Pipelined DCD Sync SRAM | |
| Fabricantes | Cypress Semiconductor | |
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CY7C1366C
CY7C1367C
9-Mbit (256K × 36/512K × 18)
Pipelined DCD Sync SRAM
9-Mbit (256K × 36/512K × 18) Pipelined DCD Sync SRAM
Features
■ Supports bus operation up to 166 MHz
■ Available speed grade is 166 MHz
■ Registered inputs and outputs for pipelined operation
❐ Optimal for performance (double-cycle deselect)
• Depth expansion without wait state
❐ 3.3 V – 5% and + 10% core power supply (VDD)
■ 2.5 V/3.3 V I/O power supply (VDDQ)
■ Fast clock-to-output times
❐ 3.5 ns (for 166 MHz device)
■ Provide high performance 3-1-1-1 access rate
■ User-selectable burst counter supporting Intel Pentium
interleaved or linear burst sequences
■ Separate processor and controller address strobes
■ Synchronous self-timed writes
■ Asynchronous output enable
■ Available in Pb-free 100-pin TQFP and non Pb-free 119-ball
BGA package
■ IEEE 1149.1 JTAG-compatible boundary scan
■ “ZZ” sleep mode option
Functional Description
The CY7C1366C/CY7C1367C SRAM integrates 256K × 36 and
512K × 18 SRAM cells with advanced synchronous peripheral
circuitry and a two-bit counter for internal burst operation. All
synchronous inputs are gated by registers controlled by a
positive-edge-triggered clock input (CLK). The synchronous
inputs include all addresses, all data inputs, address-pipelining
CchEip3[1e])n, abbulerst(CcEon1)t,rodl einppthu-tesxp(AanDsSioCn,
chip enables (CE2 and
ADSP, and ADV), write
enables (BWX, and BWE), and global write (GW). Asynchronous
inputs include the output enable (OE) and the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either address strobe processor (ADSP) or address
strobe controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed write cycle.This part supports byte write
operations (see Pin Definitions on page 6 and Partial Truth Table
for Read/Write on page 9 for further details). Write cycles can be
one to four bytes wide as controlled by the byte write control
inputs. GW active LOW causes all bytes to be written. This
device incorporates an additional pipelined enable register which
delays turning off the output buffers an additional cycle when a
deselect is executed. This feature enables depth expansion
without penalizing system performance.
The CY7C1366C/CY7C1367C operates from a +3.3 V core
power supply while all outputs operate with a +3.3 V or a +2.5 V
supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
For a complete list of related documentation, click here.
Selection Guide
Maximum access time
Maximum operating current
Maximum CMOS standby current
Description
166 MHz
3.5
180
40
Unit
ns
mA
mA
Note
1. CE3 is for 100-pin TQFP. 119-ball BGA is offered only in 2 Chip Enable.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05542 Rev. *M
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 9, 2016
1 page  
CY7C1366C
CY7C1367C
Pin Configurations (continued)
Figure 2. 119-ball BGA (14 × 22 × 2.4 mm) pinout (2 Chip Enable with JTAG)
CY7C1366C (256K × 36)
1 234567
A VDDQ
A
A ADSP A
A VDDQ
B NC/288M CE2
C NC/144M A
A ADSC A
A VDD A
A NC/576M
A NC/1G
D
DQC
DQPC
VSS
E DQC DQC VSS
F
VDDQ
DQC
VSS
NC
CE1
OE
VSS DQPB DQB
VSS
DQB
DQB
VSS
DQB
VDDQ
G DQC DQC BWC ADV BWB DQB DQB
H DQC DQC VSS
GW
VSS
DQB
DQB
J VDDQ VDD
NC
VDD
NC
VDD
VDDQ
K DQD DQD
VSS
CLK
VSS
DQA
DQA
L
DQD
DQD
BWD
NC
BWA
DQA
DQA
M VDDQ DQD
VSS
BWE
VSS
DQA
VDDQ
N DQD DQD VSS
A1
VSS
DQA
DQA
P
DQD
DQPD
VSS
A0
R NC
A
MODE
VDD
VSS DQPA DQA
NC A NC
T NC NC/72M A A A NC/36M ZZ
U VDDQ TMS
TDI
TCK
TDO
NC VDDQ
Document Number: 38-05542 Rev. *M
Page 5 of 31
5 Page 
CY7C1366C
CY7C1367C
TAP Instruction Set
Overview
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in Identification
Codes on page 16. Three of these instructions are listed as
RESERVED and should not be used. The other five instructions
are described in detail in this section.
The TAP controller used in this SRAM is not fully compliant to the
1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented.
The TAP controller cannot be used to load address data or
control signals into the SRAM and cannot preload the I/O buffers.
The SRAM does not implement the 1149.1 commands EXTEST
or INTEST or the PRELOAD portion of SAMPLE/PRELOAD;
rather, it performs a capture of the I/O ring when these
instructions are executed.
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO balls. To execute
the instruction once it is shifted in, the TAP controller needs to be
moved into the Update-IR state.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be
executed whenever the instruction register is loaded with all 0s.
EXTEST is not implemented in this SRAM TAP controller, and
therefore this device is not compliant to 1149.1. The TAP
controller does recognize an all-0 instruction.
When an EXTEST instruction is loaded into the instruction
register, the SRAM responds as if a SAMPLE/PRELOAD
instruction has been loaded. There is one difference between the
two instructions. Unlike the SAMPLE/PRELOAD instruction,
EXTEST places the SRAM outputs in a high Z state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction register
upon power up or whenever the TAP controller is given a test
logic reset state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register to
be connected between the TDI and TDO balls when the TAP
controller is in a Shift-DR state. It also places all SRAM outputs
into a high Z state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because there
is a large difference in the clock frequencies, it is possible that
during the Capture-DR state, an input or output undergoes a
transition. The TAP may then try to capture a signal while in
transition (metastable state). This does not harm the device, but
there is no guarantee as to the value that is captured.
Repeatable results may not be possible.
To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture setup plus hold
times (tCS and tCH). The SRAM clock input might not be captured
correctly if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an issue, it is
still possible to capture all other signals and simply ignore the
value of the CK and CK# captured in the boundary scan register.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
PRELOAD enables an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells prior
to the selection of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required - that is, while data captured
is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO balls. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Document Number: 38-05542 Rev. *M
Page 11 of 31
11 Page | ||
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| PDF Descargar | [ Datasheet CY7C1367C.PDF ] | |
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