|
|
PDF CY7C1363D Data sheet ( Hoja de datos )
| Número de pieza | CY7C1363D | |
| Descripción | 9-Mbit Flow-Through SRAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de CY7C1363D (archivo pdf) en la parte inferior de esta página. Total 22 Páginas | ||
|
No Preview Available !
CY7C1363D
9-Mbit (512K × 18) Flow-Through SRAM
9-Mbit (512K × 18) Flow-Through SRAM
Features
■ Supports 133 MHz bus operations
■ 512K × 18 common I/O
■ 3.3 V – 5% and +10% core power supply (VDD)
■ 2.5 V or 3.3 V I/O power supply (VDDQ)
■ Fast clock-to-output times
❐ 6.5 ns (133-MHz version)
■ Provide high performance 2-1-1-1 access rate
■ User-selectable burst counter supporting Intel Pentium
interleaved or linear burst sequences
■ Separate processor and controller address strobes
■ Synchronous self-timed write
■ Asynchronous output enable
■ Available in Pb-free 100-pin TQFP package
■ TQFP available with 3-chip enable
■ “ZZ” sleep mode option
Functional Description
The CY7C1363D is a 3.3 V, 512K × 18 synchronous flow-through
SRAM, respectively designed to interface with high speed
microprocessors with minimum glue logic. Maximum access
delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip
counter captures the first address in a burst and increments the
address automatically for the rest of the burst access. All
synchronous inputs are gated by registers controlled by a
positive-edge-triggered clock input (CLK). The synchronous
inputs include all addresses, all data inputs, address-pipelining
CchEip3[1e])n, abbulerst(CcEon1)t,rodl einppthu-tesxp(AanDsSioCn,
chip enables (CE2 and
ADSP, and ADV), write
enables (BWx, and BWE), and global write (GW). Asynchronous
inputs include the output enable (OE) and the ZZ pin.
The CY7C1363D enables either interleaved or linear burst
sequences, selected by the MODE input pin. A HIGH selects an
interleaved burst sequence, while a LOW selects a linear burst
sequence. Burst accesses can be initiated with the processor
address strobe (ADSP) or the cache controller address strobe
(ADSC) inputs. Address advancement is controlled by the
address advancement (ADV) input.
Addresses and chip enables are registered at rising edge of
clock when either address strobe processor (ADSP) or address
strobe controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
advance pin (ADV).
The CY7C1363D operates from a +3.3 V core power supply
while all outputs may operate with either a +2.5 or +3.3 V supply.
All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
For a complete list of related documentation, click here.
Selection Guide
Maximum access time
Maximum operating current
Maximum CMOS standby current
Description
Industrial
133 MHz
6.5
250
40
Unit
ns
mA
mA
Note
1. CE3 is for A version of 100-pin TQFP (3 Chip Enable Option).
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-86215 Rev. *D
• San Jose, CA 95134-1709 • 408-943-2600
Revised June 23, 2016
1 page  
CY7C1363D
Pin Definitions
Name
A0, A1, A
BWA,BWB
GW
CLK
CE1
CE2
CE3[2]
OE
ADV
ADSP
ADSC
BWE
ZZ
DQs
DQPX
MODE
VDD
I/O Description
Input- Address inputs used to select one of the address locations. Sampled at the rising edge of the CLK
synchronous if ADSP or ADSC is active LOW, and CE1, CE2, and CE3[2] are sampled active. A[1:0] feed the 2-bit
counter.
Input- Byte write select inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled
synchronous on the rising edge of CLK.
Input- Global write enable input, active LOW. When asserted LOW on the rising edge of CLK, a global write is
synchronous conducted (all bytes are written, regardless of the values on BWX and BWE).
Input-
clock
Clock input. Used to capture all synchronous inputs to the device. Also used to increment the burst
counter when ADV is asserted LOW, during a burst operation.
Input-
synchronous
Chip enable
and CE3[2] to
1 input, active
select/deselect
LOW. Sampled on the rising edge
the device. ADSP is ignored if CE1
of
is
CLK. Used
HIGH. CE1
in
is
conjunction with CE2
sampled only when a
new external address is loaded.
Input-
synchronous
Chip enable
and CE3[2] to
2 input, active
select/deselect
HIGH. Sampled
the device. CE2
on the rising edge of CLK. Used in conjunction with CE1
is sampled only when a new external address is loaded.
Input- Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
synchronous and CE2 to select/deselect the device. CE3 is sampled only when a new external address is loaded.
Input- Output enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW,
asynchronous the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tristated, and act as input data pins.
OE is masked during the first clock of a read cycle when emerging from a deselected state.
Input- Advance input signal, sampled on the rising edge of CLK. When asserted, it automatically
synchronous increments the address in a burst cycle.
Input- Address strobe from processor, sampled on the rising edge of CLK, active LOW. When asserted
synchronous LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is
ignored when CE1 is deasserted HIGH.
Input- Address strobe from controller, sampled on the rising edge of CLK, active LOW. When asserted
synchronous LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
Input- Byte write enable input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted
synchronous LOW to conduct a byte write.
Input- ZZ “sleep” input, active HIGH. When asserted HIGH places the device in a non-time-critical “sleep”
asynchronous condition with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ
pin has an internal pull down.
I/O- Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the
synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the
addresses presented during the previous clock rise of the read cycle. The direction of the pins is
controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX
are placed in a tristate condition.The outputs are automatically tristated during the data portion of a write
sequence, during the first clock when emerging from a deselected state, and when the device is
deselected, regardless of the state of OE.
I/O- Bidirectional data parity I/O lines. Functionally, these signals are identical to DQs. During write
synchronous sequences, DQPX is controlled by BWX correspondingly.
Input-
static
Selects burst order. When tied to GND selects linear burst sequence. When tied to VDD or left floating
selects interleaved burst sequence. This is a strap pin and should remain static during device operation.
Mode Pin has an internal pull-up.
Power supply Power supply inputs to the core of the device.
Note
2. CE3 is for A version of 100-pin TQFP (3 Chip Enable Option).
Document Number: 001-86215 Rev. *D
Page 5 of 22
5 Page 
CY7C1363D
Electrical Characteristics (continued)
Over the Operating Range
Parameter [12, 13]
Description
IDD VDD operating supply current
ISB1 Automatic CE power-down
current – TTL inputs
ISB2 Automatic CE power-down
current – CMOS inputs
ISB3 Automatic CE power-down
current – CMOS inputs
ISB4 Automatic CE power-down
current – TTL inputs
Test Conditions
VDD = Max, IOUT = 0 mA,
f = fMAX = 1/tCYC
Max VDD, device deselected,
VIN> VIH or VIN < VIL, f = fMAX,
inputs switching
7.5 ns cycle,
133 MHz
7.5 ns cycle,
133 MHz
Max VDD, device deselected, 7.5 ns cycle,
VIN > VDD – 0.3 V or VIN < 0.3 V, 133 MHz
f = 0, inputs static
Max VDD, device deselected, 7.5 ns cycle,
VIN > VDDQ – 0.3 V or VIN < 0.3 V, 133 MHz
f = fMAX, inputs switching
Max VDD, device deselected,
VIN > VIH or VIN < VIL,
f = 0, inputs static
7.5 ns cycle,
133 MHz
Min
–
–
–
–
–
Max Unit
250 mA
110 mA
40 mA
100 mA
40 mA
Capacitance
Parameter [14]
Description
CIN
CCLK
CI/O
Input capacitance
Clock input capacitance
Input/output capacitance
Thermal Resistance
Parameter [14]
Description
JA
JC
Thermal resistance
(junction to ambient)
Thermal resistance
(junction to case)
Test Conditions
TA = 25 C, f = 1 MHz,
VDD = 3.3 V, VDDQ = 2.5 V
100-pin TQFP
Max
5
5
5
Unit
pF
pF
pF
Test Conditions
100-pin TQFP
Package
Unit
Test conditions follow standard test methods and
procedures for measuring thermal impedance, according
to EIA/JESD51
29.41
6.31
°C/W
°C/W
Note
14. Tested initially and after any design or process change that may affect these parameters.
Document Number: 001-86215 Rev. *D
Page 11 of 22
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet CY7C1363D.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| CY7C1363C | (CY7C1361C / CY7C1363C) 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM | Cypress Semiconductor |
| CY7C1363D | 9-Mbit Flow-Through SRAM | Cypress Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |