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PDF CY7C1380KV33 Data sheet ( Hoja de datos )
| Número de pieza | CY7C1380KV33 | |
| Descripción | 18-Mbit Pipelined SRAM | |
| Fabricantes | Cypress Semiconductor | |
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CY7C1380KV33
CY7C1382KV33
18-Mbit (512K × 36/1M × 18)
Pipelined SRAM
18-Mbit (512K × 36/1M × 18) Pipelined SRAM
Features
■ Supports bus operation up to 250 MHz
■ Available speed grades are 250, 200, and 167 MHz
■ Registered inputs and outputs for pipelined operation
■ 3.3 V core power supply
■ 2.5 V or 3.3 V I/O power supply
■ Fast clock-to-output times
❐ 2.5 ns (for 250 MHz device)
■ Provides high performance 3-1-1-1 access rate
■ Separate processor and controller address strobes
■ Synchronous self-timed write
■ Asynchronous output enable
■ Single cycle chip deselect
■ Available in JEDEC-standard Pb-free 100-pin TQFP and non
Pb-free 165-ball FBGA package.
■ IEEE 1149.1 JTAG-Compatible Boundary Scan
■ ZZ sleep mode option
Functional Description
The CY7C1380KV33/CY7C1382KV33 SRAM integrates
524,288 × 36 and 1,048,576 × 18 SRAM cells with advanced
synchronous peripheral circuitry and a two-bit counter for
internal burst operation. All synchronous inputs are gated by
registers controlled by a positive edge triggered clock input
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining chip enable (CE1), depth-expansion
chip enables (CE2 and CE3), burst control inputs (ADSC, ADSP,
and ADV), write enables (BWX, and BWE), and global write
(GW). Asynchronous inputs include the output enable (OE) and
the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when address strobe processor (ADSP) or address strobe
controller (ADSC) are active. Subsequent burst addresses can
be internally generated as they are controlled by the advance pin
(ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed write cycle. This part supports byte write
operations (see Pin Definitions on page 6 and Truth Table on
page 10 for further details). Write cycles can be one to two or four
bytes wide as controlled by the byte write control inputs. GW
when active LOW causes all bytes to be written.
The CY7C1380KV33/CY7C1382KV33 operates from a +3.3 V
core power supply while all outputs operate with a +2.5 or +3.3 V
power supply. All inputs and outputs are JEDEC-standard and
JESD8-5-compatible.
Selection Guide
Maximum Access Time
Maximum Operating Current
Description
250 MHz 200 MHz 167 MHz Unit
2.5 3.0 3.4 ns
× 18 180 158 143 mA
× 36 200 178 163
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-97878 Rev. *E
• San Jose, CA 95134-1709 • 408-943-2600
Revised July 1, 2016
1 page  
CY7C1380KV33
CY7C1382KV33
Pin Configurations (continued)
Figure 2. 165-ball FBGA (13 × 15 × 1.4 mm) pinout (3-Chip Enable)
CY7C1380KV33 (512K × 36)
123
A NC/288M
B NC/144M
A
A
CE1
CE2
C
DQPC
NC
VDDQ
D
DQC
DQC
VDDQ
E
DQC
DQC
VDDQ
F
DQC
DQC
VDDQ
G
DQC
DQC
VDDQ
H NC NC NC
J
DQD
DQD
VDDQ
K
DQD
DQD
VDDQ
L
DQD
DQD
VDDQ
M
DQD
DQD
VDDQ
N
DQPD
NC
VDDQ
P NC NC/72M A
R MODE NC/36M A
4
BWC
BWD
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A
A
5
BWB
BWA
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
TDI
TMS
6
CE3
CLK
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
A1
A0
7
BWE
GW
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
TDO
TCK
8
ADSC
OE
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A
A
9
ADV
ADSP
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
A
10 11
A NC
A NC/576M
NC/1G
DQB
DQB
DQB
DQB
NC
DQPB
DQB
DQB
DQB
DQB
ZZ
DQA
DQA
DQA
DQA
NC
A
DQA
DQA
DQA
DQA
DQPA
A
AA
Document Number: 001-97878 Rev. *E
Page 5 of 33
5 Page 
CY7C1380KV33
CY7C1382KV33
Truth Table for Read/Write
The Truth Table for Read/Write for CY7C1380KV33 follows. [6, 7]
Function (CY7C1380KV33)
Read
Read
Write Byte A – (DQA and DQPA)
Write Byte B – (DQB and DQPB)
Write Bytes B, A
Write Byte C – (DQC and DQPC)
Write Bytes C, A
Write Bytes C, B
Write Bytes C, B, A
Write Byte D – (DQD and DQPD)
Write Bytes D, A
Write Bytes D, B
Write Bytes D, B, A
Write Bytes D, C
Write Bytes D, C, A
Write Bytes D, C, B
Write All Bytes
Write All Bytes
GW
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
BWE
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
BWD
X
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
X
BWC
X
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
X
BWB
X
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
X
BWA
X
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
X
Truth Table for Read/Write
The Truth Table for Read/Write for CY7C1382KV33 follows. [6, 7]
Function (CY7C1382KV33)
GW
Read
Read
Write Byte A – (DQA and DQPA)
Write Byte B – (DQB and DQPB)
Write Bytes B, A
Write All Bytes
Write All Bytes
H
H
H
H
H
H
L
BWE
H
L
L
L
L
L
X
BWB
X
H
H
L
L
L
X
BWA
X
H
L
H
L
L
X
Notes
6. X = Don't Care, H = Logic HIGH, L = Logic LOW.
7. Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write is done based on which byte write is active.
Document Number: 001-97878 Rev. *E
Page 11 of 33
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CY7C1380KV33.PDF ] | |
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