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PDF CY7C1440KV25 Data sheet ( Hoja de datos )
| Número de pieza | CY7C1440KV25 | |
| Descripción | 36-Mbit (1M x 36) Pipelined Sync SRAM | |
| Fabricantes | Cypress Semiconductor | |
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CY7C1440KV25
36-Mbit (1M × 36) Pipelined Sync SRAM
36-Mbit (1M × 36) Pipelined Sync SRAM
Features
■ Supports bus operation up to 250 MHz
■ Available speed grade is 250 MHz
■ Registered inputs and outputs for pipelined operation
■ 2.5-V core power supply
■ 2.5-V I/O power supply
■ Fast clock-to-output times
❐ 2.5 ns (for 250-MHz device)
■ Provide high-performance 3-1-1-1 access rate
■ User-selectable burst counter supporting interleaved or linear
burst sequences
■ Separate processor and controller address strobes
■ Synchronous self-timed writes
■ Asynchronous output enable
■ Single-cycle Chip Deselect
■ CY7C1440KV25 available in Pb-free 165-ball FBGA package.
■ IEEE 1149.1 JTAG-Compatible Boundary Scan
■ “ZZ” Sleep Mode Option
Functional Description
The CY7C1440KV25 SRAM integrates 1M × 36 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit counter
for internal burst operation. All synchronous inputs are gated by
registers controlled by a positive-edge-triggered Clock Input
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining Chip Enable (CE1), depth-expansion
Chip Enables (CE2 and CE3), Burst Control inputs (ADSC,
ADSP, and ADV), Write Enables (BWX, and BWE), and Global
Write (GW). Asynchronous inputs include the Output Enable
(OE) and the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or Address
Strobe Controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one, two or four bytes wide as
controlled by the byte write control inputs. GW when active LOW
causes all bytes to be written.
The CY7C1440KV25 operates from a +2.5 V core power supply
while all outputs may operate with a +2.5 V supply. All inputs
and outputs are JEDEC-standard JESD8-5-compatible.
Selection Guide
Maximum access time
Maximum operating current
Description
× 36
250 MHz
2.5
240
Unit
ns
mA
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-94719 Rev. *D
• San Jose, CA 95134-1709 • 408-943-2600
Revised June 30, 2016
1 page  
CY7C1440KV25
Pin Definitions
Name
A0, A1, A
BWA, BWB, BWC,
BWD
GW
BWE
CLK
CE1
CE2
CE3
OE
ADV
ADSP
ADSC
ZZ
DQs, DQPs
VDD
VSS
VSSQ
VDDQ
I/O Description
Input-Synchronous Address Inputs used to select one of the address locations. Sampled at the rising
edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled
active. A1:A0 are fed to the two-bit counter.
Input-Synchronous Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the
SRAM. Sampled on the rising edge of CLK.
Input-Synchronous Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK,
a global write is conducted (ALL bytes are written, regardless of the values on BWX and
BWE).
Input-Synchronous Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal
must be asserted LOW to conduct a byte write.
Input-Clock
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment
the burst counter when ADV is asserted LOW, during a burst operation.
Input-Synchronous Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is
HIGH. CE1 is sampled only when a new external address is loaded.
Input-Synchronous Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE3 to select/deselect the device. CE2 is sampled only when a
new external address is loaded.
Input-Synchronous Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE2 to select/deselect the device. Not connected for BGA. Where
referenced, CE3 is assumed active throughout this document for BGA. CE3 is sampled
only when a new external address is loaded.
Input-Asynchronous Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins.
When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tristated,
and act as input data pins. OE is masked during the first clock of a read cycle when
emerging from a deselected state.
Input-Synchronous Advance Input signal, sampled on the rising edge of CLK, active LOW. When
asserted, it automatically increments the address in a burst cycle.
Input-Synchronous Address Strobe from Processor, sampled on the rising edge of CLK, active LOW.
When asserted LOW, addresses presented to the device are captured in the address
registers. A1:A0 are also loaded into the burst counter. When ADSP and ADSC are both
asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH.
Input-Synchronous Address Strobe from Controller, sampled on the rising edge of CLK, active LOW.
When asserted LOW, addresses presented to the device are captured in the address
registers. A1:A0 are also loaded into the burst counter. When ADSP and ADSC are both
asserted, only ADSP is recognized.
Input-Asynchronous ZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a
non-time-critical “sleep” condition with data integrity preserved. For normal operation, this
pin has to be LOW or left floating. ZZ pin has an internal pull-down.
I/O-Synchronous
Power Supply
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by the addresses presented during the read cycle. The direction
of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs.
When HIGH, DQs and DQPX are placed in a tristate condition.
Power supply inputs to the core of the device.
Ground
Ground for the core of the device.
I/O Ground Ground for the I/O circuitry.
I/O Power Supply Power supply for the I/O circuitry.
Document Number: 001-94719 Rev. *D
Page 5 of 30
5 Page 
CY7C1440KV25
TAP Instruction Set
Overview
Eight different instructions are possible with the three bit
instruction register. All combinations are listed in the Instruction
Codes on page 16. Three of these instructions are listed as
RESERVED and should not be used. The other five instructions
are described in detail below.
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO balls. To execute
the instruction once it is shifted in, the TAP controller needs to be
moved into the Update-IR state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is given a test
logic reset state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register to
be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. The SAMPLE Z command puts
the output bus into a High Z state until the next command is given
during the “Update IR” state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because there
is a large difference in the clock frequencies, it is possible that
during the Capture-DR state, an input or output will undergo a
transition. The TAP may then try to capture a signal while in
transition (metastable state). This will not harm the device, but
there is no guarantee as to the value that will be captured.
Repeatable results may not be possible.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture setup plus hold
times (tCS and tCH). The SRAM clock input might not be captured
correctly if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an issue, it is
still possible to capture all other signals and simply ignore the
value of the clock captured in the boundary scan register.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells prior
to the selection of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required — that is, while data captured
is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO pins. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
EXTEST
The EXTEST instruction enables the preloaded data to be driven
out through the system output pins. This instruction also selects
the boundary scan register to be connected for serial access
between the TDI and TDO in the shift-DR controller state.
EXTEST OUTPUT BUS TRISTATE
IEEE Standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tristate mode.
The boundary scan register has a special bit located at bit #89
(for 165-ball FBGA package). When this scan cell, called the
“extest output bus tristate”, is latched into the preload register
during the “Update-DR” state in the TAP controller, it will directly
control the state of the output (Q-bus) pins, when the EXTEST is
entered as the current instruction. When HIGH, it will enable the
output buffers to drive the output bus. When LOW, this bit will
place the output bus into a High Z condition.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that cell,
during the “Shift-DR” state. During “Update-DR”, the value
loaded into that shift-register cell will latch into the preload
register. When the EXTEST instruction is entered, this bit will
directly control the output Q-bus pins. Note that this bit is pre-set
HIGH to enable the output when the device is powered-up, and
also when the TAP controller is in the “Test-Logic-Reset” state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Document Number: 001-94719 Rev. *D
Page 11 of 30
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CY7C1440KV25.PDF ] | |
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