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What is CY7C1440KV25?

This electronic component, produced by the manufacturer "Cypress Semiconductor", performs the same function as "36-Mbit (1M x 36) Pipelined Sync SRAM".


CY7C1440KV25 Datasheet PDF - Cypress Semiconductor

Part Number CY7C1440KV25
Description 36-Mbit (1M x 36) Pipelined Sync SRAM
Manufacturers Cypress Semiconductor 
Logo Cypress Semiconductor Logo 


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CY7C1440KV25
36-Mbit (1M × 36) Pipelined Sync SRAM
36-Mbit (1M × 36) Pipelined Sync SRAM
Features
Supports bus operation up to 250 MHz
Available speed grade is 250 MHz
Registered inputs and outputs for pipelined operation
2.5-V core power supply
2.5-V I/O power supply
Fast clock-to-output times
2.5 ns (for 250-MHz device)
Provide high-performance 3-1-1-1 access rate
User-selectable burst counter supporting interleaved or linear
burst sequences
Separate processor and controller address strobes
Synchronous self-timed writes
Asynchronous output enable
Single-cycle Chip Deselect
CY7C1440KV25 available in Pb-free 165-ball FBGA package.
IEEE 1149.1 JTAG-Compatible Boundary Scan
“ZZ” Sleep Mode Option
Functional Description
The CY7C1440KV25 SRAM integrates 1M × 36 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit counter
for internal burst operation. All synchronous inputs are gated by
registers controlled by a positive-edge-triggered Clock Input
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining Chip Enable (CE1), depth-expansion
Chip Enables (CE2 and CE3), Burst Control inputs (ADSC,
ADSP, and ADV), Write Enables (BWX, and BWE), and Global
Write (GW). Asynchronous inputs include the Output Enable
(OE) and the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or Address
Strobe Controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one, two or four bytes wide as
controlled by the byte write control inputs. GW when active LOW
causes all bytes to be written.
The CY7C1440KV25 operates from a +2.5 V core power supply
while all outputs may operate with a +2.5 V supply. All inputs
and outputs are JEDEC-standard JESD8-5-compatible.
Selection Guide
Maximum access time
Maximum operating current
Description
× 36
250 MHz
2.5
240
Unit
ns
mA
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-94719 Rev. *D
• San Jose, CA 95134-1709 • 408-943-2600
Revised June 30, 2016

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CY7C1440KV25 equivalent
CY7C1440KV25
Pin Definitions
Name
A0, A1, A
BWA, BWB, BWC,
BWD
GW
BWE
CLK
CE1
CE2
CE3
OE
ADV
ADSP
ADSC
ZZ
DQs, DQPs
VDD
VSS
VSSQ
VDDQ
I/O Description
Input-Synchronous Address Inputs used to select one of the address locations. Sampled at the rising
edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled
active. A1:A0 are fed to the two-bit counter.
Input-Synchronous Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the
SRAM. Sampled on the rising edge of CLK.
Input-Synchronous Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK,
a global write is conducted (ALL bytes are written, regardless of the values on BWX and
BWE).
Input-Synchronous Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal
must be asserted LOW to conduct a byte write.
Input-Clock
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment
the burst counter when ADV is asserted LOW, during a burst operation.
Input-Synchronous Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is
HIGH. CE1 is sampled only when a new external address is loaded.
Input-Synchronous Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE3 to select/deselect the device. CE2 is sampled only when a
new external address is loaded.
Input-Synchronous Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE2 to select/deselect the device. Not connected for BGA. Where
referenced, CE3 is assumed active throughout this document for BGA. CE3 is sampled
only when a new external address is loaded.
Input-Asynchronous Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins.
When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tristated,
and act as input data pins. OE is masked during the first clock of a read cycle when
emerging from a deselected state.
Input-Synchronous Advance Input signal, sampled on the rising edge of CLK, active LOW. When
asserted, it automatically increments the address in a burst cycle.
Input-Synchronous Address Strobe from Processor, sampled on the rising edge of CLK, active LOW.
When asserted LOW, addresses presented to the device are captured in the address
registers. A1:A0 are also loaded into the burst counter. When ADSP and ADSC are both
asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH.
Input-Synchronous Address Strobe from Controller, sampled on the rising edge of CLK, active LOW.
When asserted LOW, addresses presented to the device are captured in the address
registers. A1:A0 are also loaded into the burst counter. When ADSP and ADSC are both
asserted, only ADSP is recognized.
Input-Asynchronous ZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a
non-time-critical “sleep” condition with data integrity preserved. For normal operation, this
pin has to be LOW or left floating. ZZ pin has an internal pull-down.
I/O-Synchronous
Power Supply
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by the addresses presented during the read cycle. The direction
of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs.
When HIGH, DQs and DQPX are placed in a tristate condition.
Power supply inputs to the core of the device.
Ground
Ground for the core of the device.
I/O Ground Ground for the I/O circuitry.
I/O Power Supply Power supply for the I/O circuitry.
Document Number: 001-94719 Rev. *D
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Part NumberDescriptionMFRS
CY7C1440KV25The function is 36-Mbit (1M x 36) Pipelined Sync SRAM. Cypress SemiconductorCypress Semiconductor

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