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What is CY7C1444KV33?

This electronic component, produced by the manufacturer "Cypress Semiconductor", performs the same function as "36-Mbit (1M x 36/2M x 18) Pipelined DCD Sync SRAM".


CY7C1444KV33 Datasheet PDF - Cypress Semiconductor

Part Number CY7C1444KV33
Description 36-Mbit (1M x 36/2M x 18) Pipelined DCD Sync SRAM
Manufacturers Cypress Semiconductor 
Logo Cypress Semiconductor Logo 


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CY7C1444KV33
CY7C1445KV33
36-Mbit (1M × 36/2M × 18)
Pipelined DCD Sync SRAM
36-Mbit (1M × 36/2M × 18) Pipelined DCD Sync SRAM
Features
Supports bus operation up to 250 MHz
Available speed grades is 250 MHz
Registered inputs and outputs for pipelined operation
Optimal for performance (double-cycle deselect)
Depth expansion without wait state
3.3-V core power supply
2.5-V or 3.3-V I/O power supply
Fast clock-to-output times
2.5 ns (for 250-MHz device)
Provide high-performance 3-1-1-1 access rate
User-selectable burst counter supporting interleaved or linear
burst sequences
Separate processor and controller address strobes
Synchronous self-timed writes
Asynchronous output enable
CY7C1444KV33,
CY7C1445KV33
available
JEDEC-standard Pb-free 100-pin TQFP packages
in
“ZZ” sleep mode option
Functional Description
The CY7C1444KV33/CY7C1445KV33 SRAMs integrate
1M × 36/2M × 18 SRAM cells with advanced synchronous
peripheral circuitry and a two-bit counter for internal burst
operation. All synchronous inputs are gated by registers
controlled by a positive-edge-triggered clock (CLK) input. The
synchronous inputs include all addresses, all data inputs,
address-pipelining chip enable (CE1), depth-expansion chip
enables (CE2 and CE3), burst control inputs (ADSC, ADSP, and
ADV), write enables (BWX, and BWE), and global write (GW).
Asynchronous inputs include the output enable (OE) and the ZZ
pin.
Addresses and chip enables are registered at rising edge of
clock when either address strobe processor (ADSP) or address
strobe controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed write cycle. This part supports byte write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to four bytes wide as controlled
by the byte write control inputs. GW active LOW causes all bytes
to be written. This device incorporates an additional pipelined
enable register which delays turning off the output buffers an
additional cycle when a deselect is executed. This feature allows
depth expansion without penalizing system performance.
The CY7C1444KV33/CY7C1445KV33 SRAMs operate from a
+3.3 V core power supply while all outputs operate with a +3.3 V
or a +2.5 V supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
Selection Guide
Maximum access time
Maximum operating current
Description
× 18
× 36
250 MHz
2.5
220
240
Unit
ns
mA
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-66678 Rev. *G
• San Jose, CA 95134-1709 • 408-943-2600
Revised July 5, 2016

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CY7C1444KV33 equivalent
CY7C1444KV33
CY7C1445KV33
Pin Definitions
Name
I/O
Description
A0, A1, A
Address inputs used to select one of the address locations. Sampled at the rising
Input-synchronous edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled
active. A1: A0 are fed to the two-bit counter..
BWA, BWB, BWC, BWD
Input-synchronous
Byte write select inputs, active LOW. Qualified with BWE to conduct byte writes to
the SRAM. Sampled on the rising edge of CLK.
Global write enable input, active LOW. When asserted LOW on the rising edge of
GW Input-synchronous CLK, a global write is conducted (all bytes are written, regardless of the values on BWX
and BWE).
BWE
Input-synchronous
Byte write enable input, active LOW. Sampled on the rising edge of CLK. This signal
must be asserted LOW to conduct a byte write.
CLK
Input-clock
Clock input. Used to capture all synchronous inputs to the device. Also used to
increment the burst counter when ADV is asserted LOW, during a burst operation.
Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in
CE1 Input-synchronous conjunction with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1
is HIGH. CE1 is sampled only when a new external address is loaded.
Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in
CE2 Input-synchronous conjunction with CE1 and CE3 to select/deselect the device. CE2 is sampled only when
a new external address is loaded.
Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in
CE3 Input-synchronous conjunction with CE1 and CE2 to select/deselect the device. CE3 is sampled only when
a new external address is loaded.
Output enable, asynchronous input, active LOW. Controls the direction of the I/O
OE
Input-asynchronous
pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, DQ pins
are tristated, and act as input data pins. OE is masked during the first clock of a read
cycle when emerging from a deselected state.
ADV
Input-synchronous
Advance input signal, sampled on the rising edge of CLK, active LOW. When
asserted, it automatically increments the address in a burst cycle.
ADSP
Input-synchronous
Address strobe from processor, sampled on the rising edge of CLK, active LOW.
When asserted LOW, addresses presented to the device are captured in the address
registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are
both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted
HIGH.
ADSC
Input-synchronous
Address strobe from controller, sampled on the rising edge of CLK, active LOW.
When asserted LOW, addresses presented to the device are captured in the address
registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are
both asserted, only ADSP is recognized.
ZZ “sleep” input, active HIGH. When asserted HIGH places the device in a
ZZ Input-asynchronous non-time-critical “sleep” condition with data integrity preserved. For normal operation,
this pin has to be LOW or left floating. ZZ pin has an internal pull-down.
DQs, DQPs
VDD
VSS
VSSQ
I/O-synchronous
Power supply
Ground
I/O ground
Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by the addresses presented during the read cycle. The
direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave
as outputs. When HIGH, DQs and DQPX are placed in a tristate condition.
Power supply inputs to the core of the device.
Ground for the core of the device.
Ground for the I/O circuitry.
Document Number: 001-66678 Rev. *G
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Featured Datasheets

Part NumberDescriptionMFRS
CY7C1444KV33The function is 36-Mbit (1M x 36/2M x 18) Pipelined DCD Sync SRAM. Cypress SemiconductorCypress Semiconductor

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