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PDF CY7C1614KV18 Data sheet ( Hoja de datos )
| Número de pieza | CY7C1614KV18 | |
| Descripción | 144-Mbit QDR II SRAM Two-Word Burst Architecture | |
| Fabricantes | Cypress Semiconductor | |
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CY7C1625KV18
CY7C1612KV18
CY7C1614KV18
144-Mbit QDR® II SRAM Two-Word
Burst Architecture
144-Mbit QDR® II SRAM Two-Word Burst Architecture
Features
■ Separate independent read and write data ports
❐ Supports concurrent transactions
■ 360-MHz clock for high bandwidth
■ Two-word burst on all accesses
■ Double data rate (DDR) interfaces on both read and write ports
(data transferred at 720 MHz) at 360 MHz
■ Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only
■ Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches
■ Echo clocks (CQ and CQ) simplify data capture in high-speed
systems
■ Single multiplexed address input bus latches address inputs
for both read and write ports
■ Separate port selects for depth expansion
■ Synchronous internally self-timed writes
■ Quad data rate (QDR®) II operates with 1.5-cycle read latency
when DOFF is asserted high
■ Operates similar to QDR I device with 1 cycle read latency when
DOFF is asserted low
■ Available in × 9, × 18, and × 36 configurations
■ Full data coherency, providing most current data
■ Core VDD = 1.8 V (± 0.1 V); I/O VDDQ = 1.4 V to VDD
❐ Supports both 1.5 V and 1.8 V I/O supply
■ Available in 165-ball fine-pitch ball grid array (FBGA) package
(15 × 17 × 1.4 mm)
■ Offered in both Pb-free and non Pb-free packages
■ Variable drive high-speed transceiver logic (HSTL) output
buffers
■ JTAG 1149.1 compatible test access port
■ Phase Locked Loop (PLL) for accurate data placement
Configurations
CY7C1625KV18 – 16 M × 9
CY7C1612KV18 – 8 M × 18
CY7C1614KV18 – 4 M × 36
Functional Description
The CY7C1625KV18, CY7C1612KV18, and CY7C1614KV18
are 1.8-V synchronous pipelined SRAMs, equipped with QDR II
architecture. QDR II architecture consists of two separate ports:
the read port and the write port to access the memory array. The
read port has dedicated data outputs to support read operations
and the write port has dedicated data inputs to support write
operations. QDR II architecture has separate data inputs and
data outputs to completely eliminate the need to ‘turn around’ the
data bus that exists with common I/O devices. Access to each
port is through a common address bus. Addresses for read and
write addresses are latched on alternate rising edges of the input
(K) clock. Accesses to the QDR II read and write ports are
completely independent of one another. To maximize data
throughput, both read and write ports are equipped with DDR
interfaces. Each address location is associated with two 9-bit
words (CY7C1625KV18), 18-bit words (CY7C1612KV18), or
36-bit words (CY7C1614KV18) that burst sequentially into or out
of the device. Because data can be transferred into and out of
the device on every rising edge of both input clocks (K and K and
C and C), memory bandwidth is maximized while simplifying
system design by eliminating bus turnarounds.
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
For a complete list of related documentation, click here.
Selection Guide
Description
Maximum operating frequency
Maximum operating current
360 MHz
360
× 9 Not Offered
× 18 1025
× 36 Not Offered
333 MHz
333
950
970
1160
300 MHz
300
880
910
1080
250 MHz
250
780
800
950
Unit
MHz
mA
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-16238 Rev. *N
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 4, 2016
1 page  
CY7C1625KV18
CY7C1612KV18
CY7C1614KV18
Pin Configurations
The pin configuration for CY7C1625KV18, CY7C1612KV18, and CY7C1614KV18 follow: [1]
Figure 1. 165-ball FBGA (15 × 17 × 1.4 mm) pinout
CY7C1625KV18 (16 M × 9)
12345678
A CQ A
A
WPS
NC
K
A RPS
B
NC NC NC
A NC/288M K
BWS0
A
C NC NC NC VSS A A A VSS
D NC D5 NC VSS VSS VSS VSS VSS
E
NC
NC
Q5
VDDQ
VSS
VSS
VSS
VDDQ
F
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
G
NC
D6
Q6
VDDQ
VDD
VSS
VDD
VDDQ
H
DOFF
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
J
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
K
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
L
NC
Q7
D7
VDDQ
VSS
VSS
VSS
VDDQ
M
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
N NC D8 NC VSS A A A VSS
P NC NC Q8 A A C A A
R
TDO
TCK
A
A
A
C
A
A
9
A
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
A
10
A
NC
NC
NC
D3
NC
NC
VREF
Q2
NC
NC
NC
NC
D0
TMS
11
CQ
Q4
D4
NC
Q3
NC
NC
ZQ
D2
NC
Q1
D1
NC
Q0
TDI
Note
1. NC/288M is not connected to the die and can be tied to any voltage level.
Document Number: 001-16238 Rev. *N
Page 5 of 33
5 Page 
CY7C1625KV18
CY7C1612KV18
CY7C1614KV18
Truth Table
The truth table for CY7C1625KV18, CY7C1612KV18, and CY7C1614KV18 follow. [2, 3, 4, 5, 6, 7]
Operation
K RPS WPS
DQ
DQ
Write cycle:
Load address on the rising edge of K;
input write data on K and K rising edges.
L–H X L D(A + 0) at K(t) D(A + 1) at K(t)
Read cycle:
Load address on the rising edge of K;
wait one and a half cycle; read data on C and C rising edges.
L–H
L X Q(A + 0) at C(t + 1) Q(A + 1) at C(t + 2)
NOP: No operation
Standby: Clock stopped
L–H H
Stopped X
H D=X
Q = High Z
X Previous state
D=X
Q = High Z
Previous state
Write Cycle Descriptions
The write cycle description table for CY7C1612KV18 follow. [2, 8]
BWS0
L
L
L
L
H
H
H
H
BWS1
L
L
H
H
L
L
H
H
KK
Comments
L–H – During the data portion of a write sequence
CY7C1612KV18 both bytes (D[17:0]) are written into the device.
– L–H During the data portion of a write sequence:
CY7C1612KV18 both bytes (D[17:0]) are written into the device.
L–H – During the data portion of a write sequence:
CY7C1612KV18 only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
– L–H During the data portion of a write sequence
CY7C1612KV18 only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
L–H – During the data portion of a write sequence
CY7C1612KV18 only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
– L–H During the data portion of a write sequence
CY7C1612KV18 only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
L–H – No data is written into the devices during this portion of a write operation.
– L–H No data is written into the devices during this portion of a write operation.
Notes
2. X = “Don't Care,” H = Logic HIGH, L = Logic LOW, represents rising edge.
3. Device powers up deselected with the outputs in a tristate condition.
4. “A” represents address location latched by the devices when transaction was initiated. A + 0, A + 1 represents the internal address sequence in the burst.
5. “t” represents the cycle at which a Read/Write operation is started. t + 1, and t + 2 are the first, and second clock cycles respectively succeeding the “t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. Ensure that when clock is stopped K = K and C = C = high. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically.
8.
Is based on a write cycle that was initiated in
long as the setup and hold requirements are
accordance
achieved.
with
the
Truth
Table.
BWS0,
BWS1,
BWS2
,and
BWS3
can
be
altered
on
different
portions
of
a
write
cycle,
as
Document Number: 001-16238 Rev. *N
Page 11 of 33
11 Page | ||
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| PDF Descargar | [ Datasheet CY7C1614KV18.PDF ] | |
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