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PDF CY7C1463BV33 Data sheet ( Hoja de datos )
| Número de pieza | CY7C1463BV33 | |
| Descripción | 36-Mbit (2 M x 18) Flow-Through SRAM | |
| Fabricantes | Cypress Semiconductor | |
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CY7C1463BV33
36-Mbit (2 M × 18) Flow-Through SRAM with
NoBL™ Architecture
36-Mbit (2 M × 18) Flow-Through SRAM with NoBL™ Architecture
Features
■ No Bus Latency™ (NoBL™) architecture eliminates dead
cycles between write and read cycles
■ Supports up to 133-MHz bus operations with zero wait states
❐ Data is transferred on every clock
■ Pin-compatible and functionally equivalent to ZBT™ devices
■ Internally self timed output buffer control to eliminate the need
to use OE
■ Registered inputs for flow through operation
■ Byte Write capability
■ 3.3 V/2.5 V I/O power supply
■ Fast clock-to-output times
❐ 6.5 ns (for 133-MHz device)
■ Clock Enable (CEN) pin to enable clock and suspend operation
■ Synchronous self timed writes
■ Asynchronous Output Enable
■ CY7C1463BV33 available in JEDEC-standard Pb-free 100-pin
TQFP package
■ Three chip enables for simple depth expansion
■ Automatic Power down feature available using ZZ mode or CE
deselect
■ Burst Capability — linear or interleaved burst order
■ Low standby power
Functional Description
The CY7C1463BV33 is a 3.3 V, 2 M × 18 Synchronous Flow
-through Burst SRAM designed specifically to support unlimited
true back-to-back Read/Write operations without the insertion of
wait states. The CY7C1463BV33 is equipped with the advanced No
Bus Latency (NoBL) logic required to enable consecutive
Read/Write operations with data being transferred on every clock
cycle. This feature dramatically improves the throughput of data
through the SRAM, especially in systems that require frequent
Write-Read transitions.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock input is qualified by the
Clock Enable (CEN) signal, which when deasserted suspends
operation and extends the previous clock cycle. Maximum
access delay from the clock rise is 6.5 ns (133-MHz device).
Write operations are controlled by the two or four Byte Write
Select (BWX) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self timed write circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. To avoid bus contention,
the output drivers are synchronously tri-stated during the data
portion of a write sequence.
For a complete list of related documentation, click here.
Selection Guide
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Description
133 MHz
6.5
310
120
Unit
ns
mA
mA
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-75212 Rev. *C
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 5, 2016
1 page  
CY7C1463BV33
Pin Definitions
Name
I/O
Description
A0, A1, A
BWA, BWB
Input- Address Inputs Used to Select one of the Address Locations. Sampled at the rising edge of the
Synchronous CLK. A[1:0] are fed to the two-bit burst counter.
Input- Byte Write Inputs, Active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the
Synchronous rising edge of CLK.
WE Input- Write Enable Input, Active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal
Synchronous must be asserted LOW to initiate a write sequence.
ADV/LD
Input- Advance/Load Input. Used to advance the on-chip address counter or load a new address. When HIGH
Synchronous (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be
loaded into the device for an access. After being deselected, ADV/LD must be driven LOW to load a
new address.
CLK Input- Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is
Clock only recognized if CEN is active LOW.
CE1 Input- Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2
Synchronous and CE3 to select/deselect the device.
CE2 Input- Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1
Synchronous and CE3 to select/deselect the device.
CE3 Input- Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
Synchronous and CE2 to select/deselect the device.
OE Input- Output Enable, Asynchronous Input, Active LOW. Combined with the synchronous logic block inside
Asynchronou the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as
s outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during
the data portion of a write sequence, during the first clock when emerging from a deselected state, when
the device is deselected.
CEN
Input- Clock Enable Input, Active LOW. When asserted LOW the Clock signal is recognized by the SRAM.
Synchronous When deasserted HIGH the Clock signal is masked. Since deasserting CEN does not deselect the
device, use CEN to extend the previous cycle when required.
ZZ Input- ZZ “Sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition with
Asynchronou data integrity preserved. During normal operation, this pin must be LOW or left floating. ZZ pin has an
s internal pull down.
DQs
I/O- Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered by the
Synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the
addresses presented during the previous clock rise of the read cycle. The direction of the pins is
controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and
DQP[A:B] are placed in a tri-state condition.The outputs are automatically tri-stated during the data portion
of a write sequence, during the first clock when emerging from a deselected state, and when the device
is deselected, regardless of the state of OE.
DQPX
MODE
VDD
VDDQ
I/O- Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQs. During write
Synchronous sequences, DQPX is controlled by BWX correspondingly.
Input Strap Mode Input. Selects the Burst Order of the Device. When tied to GND selects linear burst sequence.
Pin When tied to VDD or left floating selects interleaved burst sequence.
Power Supply Power Supply Inputs to the Core of the Device.
I/O Power Power Supply for the I/O Circuitry.
Supply
VSS Ground Ground for the Device.
NC N/A No Connects. Not internally connected to the die.
NC/72M
N/A Not Connected to the Die. Can be tied to any voltage level.
Document Number: 001-75212 Rev. *C
Page 5 of 19
5 Page 
Switching Characteristics
Over the Operating Range
Parameter [13, 14]
Description
tPOWER[15]
Clock
tCYC
tCH
tCL
Output Times
tCDV
tDOH
tCLZ
tCHZ
tOEV
tOELZ
tOEHZ
Setup Times
tAS
tALS
tWES
tCENS
tDS
tCES
Hold Times
tAH
tALH
tWEH
tCENH
tDH
tCEH
VDD(typical) to the First Access
Clock Cycle Time
Clock HIGH
Clock LOW
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
Clock to Low Z [16, 17, 18]
Clock to High Z [16, 17, 18]
OE LOW to Output Valid
OE LOW to Output Low Z [16, 17, 18]
OE HIGH to Output High Z [16, 17, 18]
Address Setup Before CLK Rise
ADV/LD Setup Before CLK Rise
WE, BWX Setup Before CLK Rise
CEN Setup Before CLK Rise
Data Input Setup Before CLK Rise
Chip Enable Setup Before CLK Rise
Address Hold After CLK Rise
ADV/LD Hold After CLK Rise
WE, BWX Hold After CLK Rise
CEN Hold After CLK Rise
Data Input Hold After CLK Rise
Chip Enable Hold After CLK Rise
CY7C1463BV33
133 MHz
Min Max
1–
Unit
ms
7.5 – ns
2.5 – ns
2.5 – ns
– 6.5 ns
2.5 – ns
2.5 – ns
– 3.8 ns
– 3.0 ns
0 – ns
– 3.0 ns
1.5 – ns
1.5 – ns
1.5 – ns
1.5 – ns
1.5 – ns
1.5 – ns
0.5 – ns
0.5 – ns
0.5 – ns
0.5 – ns
0.5 – ns
0.5 – ns
Notes
13. Timing reference level is 1.5 V when VDDQ = 3.3 V and is 1.25 V when VDDQ = 2.5 V.
14. Test conditions shown in (a) of Figure 2 on page 10 unless otherwise noted.
15. This part has a voltage regulator internally; tPOWER is the time that the power is supplied above VDD(minimum) initially, before a read or write operation can be initiated.
16. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of Figure 2 on page 10. Transition is measured ±200 mV from steady-state voltage.
17.
At any
These
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tcOoEnLdZitaionnd,
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High Z prior to Low Z under the same system conditions.
18. This parameter is sampled and not 100% tested.
Document Number: 001-75212 Rev. *C
Page 11 of 19
11 Page | ||
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| PDF Descargar | [ Datasheet CY7C1463BV33.PDF ] | |
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