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What is CY7C1462BV25?

This electronic component, produced by the manufacturer "Cypress Semiconductor", performs the same function as "36-Mbit (1 M x 36/2 M x 18) Pipelined SRAM".


CY7C1462BV25 Datasheet PDF - Cypress Semiconductor

Part Number CY7C1462BV25
Description 36-Mbit (1 M x 36/2 M x 18) Pipelined SRAM
Manufacturers Cypress Semiconductor 
Logo Cypress Semiconductor Logo 


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CY7C1460BV25
CY7C1462BV25
36-Mbit (1 M × 36/2 M × 18)
Pipelined SRAM with NoBL™ Architecture
36-Mbit (1 M × 36/2 M × 18) Pipelined SRAM with NoBL™ Architecture
Features
Pin-compatible and functionally equivalent to ZBT™
Supports 250-MHz bus operations with zero wait states
Available speed grades is 250 MHz
Internally self-timed output buffer control to eliminate the need
to use asynchronous OE
Fully registered (inputs and outputs) for pipelined operation
Byte Write capability
2.5 V core power supply
2.5 V I/O power supply
Fast clock-to-output times
2.6 ns (for 250-MHz device)
Clock enable (CEN) pin to suspend operation
Synchronous self-timed writes
CY7C1460BV25, CY7C1462BV25 available in Pb-free
165-ball FBGA package and CY7C1462BV25 available in
JEDEC-standard Pb-free 100-pin TQFP package
IEEE 1149.1 JTAG-Compatible Boundary Scan
Burst capability – linear or interleaved burst order
“ZZ” sleep mode option and stop clock option
Functional Description
The CY7C1460BV25/CY7C1462BV25 are 2.5 V,
1 M × 36/2 M × 18 synchronous pipelined burst SRAMs with No
Bus Latency™ (NoBL logic, respectively. They are designed
to support unlimited true back-to-back read/write operations with
no wait states. The CY7C1460BV25/CY7C1462BV25 are
equipped with the advanced NoBL logic required to enable
consecutive read/write operations with data being transferred on
every clock cycle. This feature dramatically improves the
throughput of data in systems that require frequent write/read
transitions. The CY7C1460BV25/CY7C1462BV25 are
pin-compatible and functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. The clock
input is qualified by the clock enable (CEN) signal, which when
deasserted suspends operation and extends the previous clock
cycle. Write operations are controlled by the byte write selects
(BWa–BWd for CY7C1460BV25 and BWa–BWb for
CY7C1462BV25) and a write enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) provide for easy bank
selection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
For a complete list of related documentation, click here.
Logic Block Diagram – CY7C1460BV25
A0, A1, A
MODE
CLK C
CEN
ADV/LD
BWa
BWb
BWc
BWd
WE
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
A1 D1
Q1 A1'
A0 D0 BURST Q0 A0'
LOGIC
ADV/LD
C
WRITE ADDRESS
REGISTER 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
E
D
A
T
A
S
T
E
E
R
I
N
O
U
T
P
U
T
B
U
F
F
E
R
S
E
G
INPUT
REGISTER 1 E
INPUT
REGISTER 0 E
DQs
DQPa
DQPb
DQPc
DQPd
OE
CE1 READ LOGIC
CE2
CE3
ZZ SLEEP
CONTROL
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-74446 Rev. *F
• San Jose, CA 95134-1709 • 408-943-2600
Revised December 24, 2015

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CY7C1462BV25 equivalent
CY7C1460BV25
CY7C1462BV25
Pin Configurations (continued)
Figure 2. 165-ball FBGA (15 × 17 × 1.4 mm) pinout
123
A NC/576M
B NC/1G
A
A
CE1
CE2
C DQPc NC VDDQ
D
DQc
DQc
VDDQ
E
DQc
DQc
VDDQ
F
DQc
DQc
VDDQ
G
DQc
DQc
VDDQ
H NC NC NC
J
DQd
DQd
VDDQ
K
DQd
DQd
VDDQ
L
DQd
DQd
VDDQ
M
DQd
DQd
VDDQ
N DQPd NC VDDQ
P NC/144M NC/72M A
R MODE A
A
CY7C1460BV25 (1 M × 36)
4 567
BWc
BWd
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A
BWb
BWa
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
TDI
CE3
CLK
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
A1
CEN
WE
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
TDO
A TMS A0 TCK
8
ADV/LD
OE
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A
A
9
A
A
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
A
10
A
A
NC
DQb
DQb
DQb
DQb
NC
DQa
DQa
DQa
DQa
NC
A
A
11
NC
NC
DQPb
DQb
DQb
DQb
DQb
ZZ
DQa
DQa
DQa
DQa
DQPa
NC/288M
A
123
A NC/576M
B NC/1G
A
A
CE1
CE2
C NC NC VDDQ
D
NC
DQb
VDDQ
E
NC
DQb
VDDQ
F
NC
DQb
VDDQ
G
NC
DQb
VDDQ
H NC NC NC
J DQb NC VDDQ
K DQb NC VDDQ
L DQb NC VDDQ
M DQb NC VDDQ
N DQPb NC VDDQ
P NC/144M NC/72M A
R MODE
A
A
CY7C1462BV25 (2 M × 18)
4
BWb
NC
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A
5
NC
BWa
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
TDI
6
CE3
CLK
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
A1
7
CEN
WE
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
TDO
A TMS A0 TCK
8
ADV/LD
OE
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A
A
9
A
A
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
A
10
A
A
NC
NC
NC
NC
NC
NC
DQa
DQa
DQa
DQa
NC
A
A
11
A
NC
DQPa
DQa
DQa
DQa
DQa
ZZ
NC
NC
NC
NC
NC
NC/288M
A
Document Number: 001-74446 Rev. *F
Page 5 of 29


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Featured Datasheets

Part NumberDescriptionMFRS
CY7C1462BV25The function is 36-Mbit (1 M x 36/2 M x 18) Pipelined SRAM. Cypress SemiconductorCypress Semiconductor

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