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PDF CY7C1354CV25 Data sheet ( Hoja de datos )
| Número de pieza | CY7C1354CV25 | |
| Descripción | 9-Mbit (256K x 36/512K x 18) Pipelined SRAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY7C1354CV25
CY7C1356CV25
9-Mbit (256K × 36/512K × 18)
Pipelined SRAM with NoBL™ Architecture
9-Mbit (256K × 36/512K × 18) Pipelined SRAM with NoBL™ Architecture
Features
■ Pin-compatible with and functionally equivalent to ZBT™
■ Supports 250-MHz bus operations with zero wait states
■ Available speed grades are 250, 200, and 166 MHz
■ Internally self-timed output buffer control to eliminate the need
to use asynchronous OE
■ Fully registered (inputs and outputs) for pipelined operation
■ Byte write capability
■ Single 2.5 V power supply (VDD)
■ Fast clock-to-output times
❐ 2.8 ns (for 250-MHz device)
■ Clock enable (CEN) pin to suspend operation
■ Synchronous self-timed writes
■ Available in Pb-free 100-pin TQFP package, Pb-free and
non Pb-free 119-ball BGA package and 165-ball FBGA
package
■ IEEE 1149.1 JTAG-compatible boundary scan
■ Burst capability–linear or interleaved burst order
■ “ZZ” sleep mode option and stop clock option
Functional Description
The CY7C1354CV25/CY7C1356CV25[1] are 2.5 V,
256K × 36/512K × 18 synchronous pipelined burst SRAMs with
No Bus Latency™ (NoBL logic, respectively. They are
designed to support unlimited true back-to-back read/write
operations with no wait states. The
CY7C1354CV25/CY7C1356CV25 are equipped with the
advanced (NoBL) logic required to enable consecutive
read/write operations with data being transferred on every clock
cycle. This feature dramatically improves the throughput of data
in systems that require frequent write/read transitions. The
CY7C1354CV25/CY7C1356CV25 are pin-compatible with and
functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. The clock
input is qualified by the clock enable (CEN) signal, which when
deasserted suspends operation and extends the previous clock
cycle.
Write operations are controlled by the byte write selects
(BWa–BWd for CY7C1354CV25 and BWa–BWb for
CY7C1356CV25) and a write enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated during
the data portion of a write sequence.
For a complete list of related documentation, click here.
Selection Guide
Maximum access time
Maximum operating current
Maximum CMOS standby current
Description
250 MHz
2.8
250
40
200 MHz
3.2
220
40
166 MHz
3.5
180
40
Unit
ns
mA
mA
Note
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05537 Rev. *Q
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 4, 2016
1 page  
CY7C1354CV25
CY7C1356CV25
Pin Configurations
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout
DQPc
DQc
DQc
VDDQ
VSS
DQc
DQc
DQc
DQc
VSS
VDDQ
DQc
DQc
NC
VDD
NC
VSS
DQd
DQd
VDDQ
VSS
DQd
DQd
DQd
DQd
VSS
VDDQ
DQd
DQd
DQPd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1354CV25
(256K × 36)
80 DQPb NC 1
79 DQb
NC 2
78 DQb NC 3
77 VDDQ VDDQ 4
76 VSS
VSS
5
75 DQb NC 6
74 DQb
NC 7
73 DQb DQb 8
72 DQb DQb 9
71
70
VSS
VDDQ
VSS
VDDQ
10
11
69 DQb DQb 12
68 DQb DQb 13
67
66
VSS
NC
NC
VDD
14
15
65 VDD
64 ZZ
NC
VSS
63 DQa DQb
16
17
18
62
61
60
DQa
VDDQ
VSS
DQb
VDDQ
VSS
19
20
21
59 DQa DQb 22
58 DQa DQb 23
57 DQa DQPb 24
56 DQa NC 25
55
54
VSS
VDDQ
VVDSDSQ
26
27
53 DQa NC 28
52 DQa NC 29
51 DQPa NC 30
CY7C1356CV25
(512K × 18)
80 A
79 NC
78 NC
77 VDDQ
76 VSS
75 NC
74 DQPa
73 DQa
72 DQa
71 VSS
70 VDDQ
69 DQa
68 DQa
67 VSS
66 NC
65 VDD
64 ZZ
63 DQa
62 DQa
61 VDDQ
60 VSS
59 DQa
58 DQa
57 NC
56 NC
55 VSS
54 VDDQ
53 NC
52 NC
51 NC
Document Number: 38-05537 Rev. *Q
Page 5 of 35
5 Page 
CY7C1354CV25
CY7C1356CV25
Truth Table
The truth table for CY7C1354CV25/CY7C1356CV25 follows. [2, 3, 4, 5, 6, 7, 8]
Operation
Deselect cycle
Continue deselect cycle
Address used CE ZZ ADV/LD WE BWx OE CEN CLK
None
H L L X X X L L–H
None
X L H X X X L L–H
DQ
Tri-state
Tri-state
Read cycle (begin burst)
Read cycle (continue burst)
NOP/dummy read (begin burst)
Dummy read (continue burst)
Write cycle (begin burst)
Write cycle (continue burst)
NOP/write abort (begin burst)
External L L L H X L L L–H Data out (Q)
Next
X L H X X L L L–H Data out (Q)
External L L L H X H L L–H Tri-state
Next
X L H X X H L L–H Tri-state
External L L L L L X L L–H Data in (D)
Next
X L H X L X L L–H Data in (D)
None
L L L L H X L L–H Tri-state
Write abort (continue burst)
Ignore clock edge (stall)
Next
X L H X H X L L–H Tri-state
Current X L X X X X H L–H
–
Sleep mode
None
X H X X X X X X Tri-state
Notes
2. X = “Don’t Care”, H = Logic HIGH, L = Logic LOW, CE stands for all chip enables active. BWx = L signifies at least one byte write select is active, BWx = Valid signifies
that the desired byte write selects are asserted, see Write Cycle Description table for details.
3. Write is defined by WE and BWX. See Write Cycle Description table for details.
4. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.
5. The DQ and DQP pins are controlled by the current cycle and the OE signal.
6. CEN = H inserts wait states.
7. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.
8.
OE is asynchronous
inactive or when the
and is not sampled with the clock rise. It is masked internally
device is deselected, and DQs = data when OE is active.
during
write
cycles.
During
a
read
cycle
DQs
and
DQPX
=
tri-state
when
OE
is
Document Number: 38-05537 Rev. *Q
Page 11 of 35
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CY7C1354CV25.PDF ] | |
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