CY7C1353G Datasheet PDF - Cypress Semiconductor
| Part Number | CY7C1353G | |
| Description | 4-Mbit (256K x 18) Flow-Through SRAM | |
| Manufacturers | Cypress Semiconductor | |
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CY7C1353G
4-Mbit (256K × 18) Flow-Through SRAM
with NoBL™ Architecture
4-Mbit (256K × 18) Flow-Through SRAM with NoBL™ Architecture
Features
■ Supports up to 100-MHz bus operations with zero wait states
❐ Data is transferred on every clock
■ Pin compatible and functionally equivalent to ZBT™ devices
■ Internally self timed output buffer control to eliminate the need
to use OE
■ Registered inputs for flow-through operation
■ Byte write capability
■ 256K × 18 common I/O architecture
■ 2.5 V/3.3 V I/O power supply (VDDQ)
■ Fast clock-to-output times
❐ 8.0 ns (for 100-MHz device)
■ Clock enable (CEN) pin to suspend operation
■ Synchronous self timed writes
■ Asynchronous output enable
■ Available in Pb-free 100-pin TQFP package
■ Burst capability – linear or interleaved burst order
■ Low standby power
Logic Block Diagram
Functional Description
The CY7C1353G is a 3.3 V, 256K × 18 synchronous
flow-through burst SRAM designed specifically to support
unlimited true back-to-back read/write operations without the
insertion of wait states. The CY7C1353G is equipped with the
advanced No Bus Latency™ (NoBL™) logic required to enable
consecutive read/write operations with data being transferred on
every clock cycle. This feature dramatically improves the
throughput of data through the SRAM, especially in systems that
require frequent write-read transitions.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock input is qualified by the
clock enable (CEN) signal, which when deasserted suspends
operation and extends the previous clock cycle. Maximum
access delay from the clock rise is 8.0 ns (100-MHz device).
Write operations are controlled by the two byte write select
(BW[A:B]) and a write enable (WE) input. All writes are conducted
with on-chip synchronous self timed write circuitry.
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) provide for easy bank
selection and output tri-state control. To avoid bus contention,
the output drivers are synchronously tri-stated during the data
portion of a write sequence.
For a complete list of related documentation, click here.
A0, A1, A
MODE
CLK C
CEN
CE
ADV/LD
BWA
BWB
WE
ADDRESS
REGISTER
A1
A0
D1
D0
ADV/LD
C
WRITE ADDRESS
REGISTER
Q1
Q0
A1'
A0'
BURST
LOGIC
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
O
U
T
DP
AU
TT
A
B
SU
TF
EF
EE
RR
IS
NE
G
DQs
DQPA
DQPB
OE
CE1 READ LOGIC
CE2
CE3
ZZ SLEEP
CONTROL
INPUT E
REGISTER
Errata: For information on silicon errata, see "Errata" on page 16. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05515 Rev. *P
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 7, 2016
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CY7C1353G
Pin Definitions (continued)
Name
I/O
Description
DQP[A:B]
MODE
I/O- Bidirectional data parity I/O lines. Functionally, these signals are identical to DQs. During write
synchronous sequences, DQP[A:B] is controlled by BWx correspondingly.
Input strap pin MODE input. Selects the burst order of the device.
When tied to GND selects linear burst sequence. When tied to VDD or left floating selects interleaved
burst sequence.
VDD
VDDQ
Power supply Power supply inputs to the core of the device.
I/O power Power supply for the I/O circuitry.
supply
VSS
NC, NC/9M,
NC/18M,
NC/36M,
NC/72M,
NC/144M,
NC/288M
Ground
–
Ground for the device.
No Connects. Not internally connected to the die. NC/9M, NC/18M, NC/72M, NC/144M, NC/288M, are
address expansion pins are not internally connected to the die.
Functional Overview
The CY7C1353G is a synchronous flow-through burst SRAM
designed specifically to eliminate wait states during write-read
transitions. All synchronous inputs pass through input registers
controlled by the rising edge of the clock. The clock signal is
qualified with the clock enable input signal (CEN). If CEN is
HIGH, the clock signal is not recognized and all internal states
are maintained. All synchronous operations are qualified with
CEN. Maximum access delay from the clock rise (tCDV) is 8.0 ns
(100-MHz device).
Accesses can be initiated by asserting all three chip enables
(CE1, CE2, CE3) active at the rising edge of the clock. If clock
enable (CEN) is active LOW and ADV/LD is asserted LOW, the
address presented to the device is latched. The access can
either be a read or write operation, depending on the status of
the write enable (WE). BW[A:B] can be used to conduct byte write
operations.
Write operations are qualified by the write enable (WE). All writes
are simplified with on-chip synchronous self timed write circuitry.
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) simplify depth expansion. All
operations (reads, writes, and deselects) are pipe lined. ADV/LD
must be driven LOW after the device has been deselected to
load a new address for the next operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are all asserted active, (3) the write enable input signal
WE is deasserted HIGH, and 4) ADV/LD is asserted LOW. The
address presented to the address inputs is latched into the
address register and presented to the memory array and control
logic. The control logic determines that a read access is in
progress and allows the requested data to propagate to the
output buffers. The data is available within 8.0 ns (100-MHz
device) provided OE is active LOW. After the first clock of the
read access, the output buffers are controlled by OE and the
internal control logic. OE must be driven LOW in order for the
device to drive out the requested data. On the subsequent clock,
another operation (read/write/deselect) can be initiated. When
the SRAM is deselected at clock rise by one of the chip enable
signals, its output is tri-stated immediately.
Burst Read Accesses
The CY7C1353G has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to four
reads without reasserting the address inputs. ADV/LD must be
driven LOW to load a new address into the SRAM, as described
in the Single Read Accesses section. The sequence of the burst
counter is determined by the MODE input signal. A LOW input
on MODE selects a linear burst mode, a HIGH selects an
interleaved burst sequence. Both burst counters use A0 and A1
in the burst sequence, and wraps around when incremented
sufficiently. A HIGH input on ADV/LD increments the internal
burst counter regardless of the state of chip enable inputs or WE.
WE is latched at the beginning of a burst cycle. Therefore, the
type of access (read or write) is maintained throughout the burst
sequence.
Single Write Accesses
Write access are initiated when these conditions are satisfied at
clock rise:
■ CEN is asserted LOW
■ CE1, CE2, and CE3 are all asserted active
■ The write signal WE is asserted LOW.
The address presented to the address bus is loaded into the
address register. The write signals are latched into the control
logic block. The data lines are automatically tri-stated regardless
of the state of the OE input signal. This allows the external logic
to present the data on DQs and DQP[A:B].
On the next clock rise the data presented to DQs and DQP[A:B]
(or a subset for byte write operations, see truth table for details)
inputs is latched into the device and the write is complete.
Additional accesses (read/write/deselect) can be initiated on this
cycle.
Document Number: 38-05515 Rev. *P
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