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PDF CY7C1351G Data sheet ( Hoja de datos )
| Número de pieza | CY7C1351G | |
| Descripción | 4-Mbit (128K x 36) Flow-Through SRAM | |
| Fabricantes | Cypress Semiconductor | |
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CY7C1351G
4-Mbit (128K × 36) Flow-Through SRAM
with NoBL™ Architecture
4-Mbit (128K × 36) Flow-Through SRAM with NoBL™ Architecture
Features
■ Can support up to 133-MHz bus operations with zero wait
states
❐ Data is transferred on every clock
■ Pin compatible and functionally equivalent to ZBT™ devices
■ Internally self-timed output buffer control to eliminate the need
to use OE
■ Registered inputs for flow-through operation
■ Byte write capability
■ 128 K × 36 common I/O architecture
■ 2.5 V/3.3 V I/O power supply (VDDQ)
■ Fast clock-to-output times
❐ 6.5 ns (for 133-MHz device)
■ Clock enable (CEN) pin to suspend operation
■ Synchronous self-timed writes
■ Asynchronous output enable
■ Available in Pb-free 100-pin TQFP package
■ Burst capability – linear or interleaved burst order
■ Low standby power
Functional Description
The CY7C1351G is a 3.3 V, 128K × 36 synchronous flow-through
burst SRAM designed specifically to support unlimited true
back-to-back read/write operations without the insertion of wait
states. The CY7C1351G is equipped with the advanced No Bus
Latency™ (NoBL™) logic required to enable consecutive
Read/Write operations with data being transferred on every clock
cycle. This feature dramatically improves the throughput of data
through the SRAM, especially in systems that require frequent
write-read transitions.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock input is qualified by the
clock enable (CEN) signal, which when deasserted suspends
operation and extends the previous clock cycle. Maximum
access delay from the clock rise is 6.5 ns (133-MHz device).
Write operations are controlled by the four byte write select
(BW[A:D]) and a write enable (WE) input. All writes are conducted
with on-chip synchronous self-timed write circuitry.
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) provide for easy bank
selection and output tristate control. In order to avoid bus
contention, the output drivers are synchronously tristated during
the data portion of a write sequence.
For a complete list of related documentation, click here.
Selection Guide
Maximum access time
Maximum operating current
Maximum CMOS standby current
Description
133 MHz
6.5
225
40
100 MHz
8.0
205
40
Unit
ns
mA
mA
Errata: For information on silicon errata, see "Errata" on page 19. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05513 Rev. *Q
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 3, 2016
1 page  
CY7C1351G
Pin Definitions
Name
A0, A1, A
BW[A:D]
WE
ADV/LD
CLK
CE1
CE2
CE3
OE
CEN
ZZ[2]
I/O Description
Input- Address inputs used to select one of the 128 K address locations. Sampled at the rising edge of
synchronous the CLK. A[1:0] are fed to the two-bit burst counter.
Input- Byte write inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the rising
synchronous edge of CLK.
Input- Write enable input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal
synchronous must be asserted LOW to initiate a write sequence.
Input- Advance/load input. Used to advance the on-chip address counter or load a new address. When HIGH
synchronous (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be
loaded into the device for an access. After being deselected, ADV/LD should be driven LOW in order to
load a new address.
Input-clock Clock input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is
only recognized if CEN is active LOW.
Input- Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2,
synchronous and CE3 to select/deselect the device.
Input- Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1
synchronous and CE3 to select/deselect the device.
Input- Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
synchronous and CE2 to select/deselect the device.
Input- Output enable, asynchronous input, active LOW. Combined with the synchronous logic block inside
asynchronous the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as
outputs. When deasserted HIGH, I/O pins are tristated, and act as input data pins. OE is masked during
the data portion of a write sequence, during the first clock when emerging from a deselected state, when
the device has been deselected.
Input- Clock enable input, active LOW. When asserted LOW the clock signal is recognized by the SRAM.
synchronous When deasserted HIGH the clock signal is masked. Since deasserting CEN does not deselect the device,
CEN can be used to extend the previous cycle when required.
Input- ZZ “sleep” input. This active HIGH input places the device in a non-time critical “sleep” condition with data
asynchronous integrity preserved. During normal operation, this pin has to be low or left floating. ZZ pin has an internal
pull-down.
Note
2. Errata: The ZZ pin (Pin 64) needs to be externally connected to ground. For more information, see "Errata" on page 19.
Document Number: 38-05513 Rev. *Q
Page 5 of 22
5 Page 
CY7C1351G
Electrical Characteristics (continued)
Over the Operating Range
Parameter [11, 12]
Description
ISB3 Automatic CE power-down
current – CMOS inputs
ISB4 Automatic CE power-down
current – TTL inputs
Test Conditions
VDD = Max, device deselected, 7.5-ns cycle,
VIN > VDDQ – 0.3 V or VIN < 0.3 V, 133 MHz
f = fMAX, inputs switching
10-ns cycle,
100 MHz
VDD = Max, device deselected, All speeds
VIN > VIH or V IN < VIL,
f = 0, inputs static
Min
–
–
–
Max Unit
75 mA
65 mA
45 mA
Capacitance
Parameter [13]
Description
CIN
CCLOCK
CI/O
Input capacitance
Clock input capacitance
I/O capacitance
Thermal Resistance
Parameter [13]
Description
JA Thermal resistance
(junction to ambient)
JC Thermal resistance
(junction to case)
Test Conditions
TA = 25 °C, f = 1 MHz,
VDD = 3.3 V, VDDQ=3.3 V
100-pin TQFP
Max
5
5
5
Unit
pF
pF
pF
Test Conditions
100-pin TQFP
Package
Unit
Test conditions follow standard test methods and
procedures for measuring thermal impedance, per
EIA/JESD51.
30.32
6.85
°C/W
°C/W
Note
13. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 38-05513 Rev. *Q
Page 11 of 22
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