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PDF CY7C1350G Data sheet ( Hoja de datos )
| Número de pieza | CY7C1350G | |
| Descripción | 4-Mbit (128K x 36) Pipelined SRAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY7C1350G
4-Mbit (128K × 36) Pipelined SRAM
with NoBL™ Architecture
4-Mbit (128K × 36) Pipelined SRAM with NoBL™ Architecture
Features
■ Pin compatible and functionally equivalent to ZBT™ devices
■ Internally self-timed output buffer control to eliminate the need
to use OE
■ Byte write capability
■ 128K × 36 common I/O architecture
■ 3.3 V power supply (VDD)
■ 2.5 V/3.3 V I/O power supply (VDDQ)
■ Fast clock-to-output times
❐ 2.8 ns (for 200-MHz device)
■ Clock enable (CEN) pin to suspend operation
■ Synchronous self-timed writes
■ Asynchronous output enable (OE)
■ Available in Pb-free 100-pin TQFP package, Pb-free and
non Pb-free 119-ball BGA package
■ Burst capability – linear or interleaved burst order
■ “ZZ” sleep mode option
Logic Block Diagram
Functional Description
The CY7C1350G is a 3.3 V, 128K × 36 synchronous-pipelined
burst SRAM designed specifically to support unlimited true
back-to-back read/write operations without the insertion of wait
states. The CY7C1350G is equipped with the advanced No Bus
Latency™ (NoBL™) logic required to enable consecutive
read/write operations with data being transferred on every clock
cycle. This feature dramatically improves the throughput of the
SRAM, especially in systems that require frequent write/read
transitions.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. The clock
input is qualified by the clock enable (CEN) signal, which, when
deasserted, suspends operation and extends the previous clock
cycle. Maximum access delay from the clock rise is 2.8 ns
(200-MHz device).
Write operations are controlled by the four byte write select
(BW[A:D]) and a write enable (WE) input. All writes are conducted
with on-chip synchronous self-timed write circuitry.
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) provide for easy bank
selection and output tristate control. In order to avoid bus
contention, the output drivers are synchronously tri-stated during
the data portion of a write sequence.
For a complete list of related documentation, click here.
A0, A1, A
MODE
CLK C
CEN
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
A1 D1
Q1 A1'
A0 D0 BURST Q0 A0'
LOGIC
ADV/LD
C
WRITE ADDRESS
REGISTER 2
ADV/LD
BWA
BWB
BWC
BWD
WE
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
E
D
A
T
A
S
T
E
E
R
I
N
O
U
T
P
U
T
B
U
F
F
E
R
S
E
G
DQs
DQPA
DQPB
DQPC
DQPD
INPUT
REGISTER 1 E
INPUT
REGISTER 0 E
OE
CE1 READ LOGIC
CE2
CE3
ZZ SLEEP
CONTROL
Errata: For information on silicon errata, see "Errata" on page 19. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05524 Rev. *Q
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 7, 2016
1 page  
CY7C1350G
Pin Definitions
Name
A0, A1, A
BW[A:D]
WE
ADV/LD
CLK
CE1
CE2
CE3
OE
CEN
ZZ[3]
DQs
DQP[A:D]
MODE
VDD
VDDQ
VSS
NC
I/O Description
Input- Address inputs used to select one of the 128 K address locations. Sampled at the rising edge of
synchronous the CLK. A[1:0] are fed to the two-bit burst counter.
Input- Byte write inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the rising
synchronous edge of CLK.
Input- Write enable input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal
synchronous must be asserted LOW to initiate a write sequence.
Input- Advance/load input. Used to advance the on-chip address counter or load a new address. When HIGH
synchronous (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be
loaded into the device for an access. After being deselected, ADV/LD should be driven LOW in order to
load a new address.
Input-clock Clock input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is
only recognized if CEN is active LOW.
Input- Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2
synchronous and CE3 to select/deselect the device.
Input- Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1
synchronous and CE3 to select/deselect the device.
Input- Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
synchronous and CE2 to select/deselect the device.
Input- Output enable, asynchronous input, active LOW. Combined with the synchronous logic block inside
asynchronous the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as
outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during
the data portion of a write sequence, during the first clock when emerging from a deselected state, when
the device has been deselected.
Input- Clock enable input, active LOW. When asserted LOW the Clock signal is recognized by the SRAM.
synchronous When deasserted HIGH the clock signal is masked. Since deasserting CEN does not deselect the device,
CEN can be used to extend the previous cycle when required.
Input- ZZ “sleep” input. This active HIGH input places the device in a non-time critical “sleep” condition with
asynchronous data integrity preserved. During normal operation, this pin has to be low or left floating. ZZ pin has an
internal pull-down.
I/O- Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the
synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the
address during the clock rise of the read cycle. The direction of the pins is controlled by OE and the
internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH, DQs and
DQPX are placed in a tristate condition. The outputs are automatically tri-stated during the data portion of
a write sequence, during the first clock when emerging from a deselected state, and when the device is
deselected, regardless of the state of OE.
I/O- Bidirectional data parity I/O lines. Functionally, these signals are identical to DQs. During write
synchronous sequences, DQP[A:D] is controlled by BW[A:D] correspondingly.
Input Mode input. Selects the burst order of the device. When tied to GND selects linear burst sequence.
strap pin When tied to VDD or left floating selects interleaved burst sequence.
Power supply Power supply inputs to the core of the device.
I/O power Power supply for the I/O circuitry.
supply
Ground Ground for the device.
– No Connects. Not internally connected to the die. 9M, 18M, 36M, 72M, 144M and 288M are address
expansion pins in this device and will be used as address pins in their respective densities.
Note
3. Errata: The ZZ pin needs to be externally connected to ground. For more information, see "Errata" on page 19.
Document Number: 38-05524 Rev. *Q
Page 5 of 22
5 Page 
CY7C1350G
Electrical Characteristics (continued)
Over the Operating Range
Parameter [14, 15]
Description
ISB3 Automatic CE power-down
current – CMOS inputs
ISB4 Automatic CE power-down
current – TTL inputs
Test Conditions
VDD = Max, device deselected, 5-ns cycle,
VIN 0.3 V or VIN > VDDQ – 0.3 V, 200 MHz
f = fMAX = 1/tCYC
7.5-ns cycle,
133 MHz
VDD = Max, device deselected, All speeds
VIN VIH or VIN VIL, f = 0
Min
–
–
–
Max Unit
95 mA
75 mA
45 mA
Capacitance
Parameter [16]
Description
CIN
CCLK
CI/O
Input capacitance
Clock input capacitance
Input/Output capacitance
Test Conditions
TA = 25 °C, f = 1 MHz,
VDD = 3.3 V, VDDQ = 3.3 V
100-pin TQFP 119-ball BGA
Max Max
55
55
57
Unit
pF
pF
pF
Thermal Resistance
Parameter [16]
Description
JA Thermal resistance
(junction to ambient)
JC Thermal resistance
(junction to case)
Test Conditions
100-pin TQFP 119-ball BGA
Package
Package
Unit
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA/JESD51.
30.32
6.85
34.1 °C/W
14.0 °C/W
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms
3.3 V I/O Test Load
OUTPUT
Z0 = 50
3.3 V
OUTPUT
RL = 50
5 pF
VT = 1.5 V
(a)
2.5 V I/O Test Load
INCLUDING
JIG AND
SCOPE
R = 317
R = 351
(b)
VDDQ
GND
10%
1 ns
ALL INPUT PULSES
90%
(c)
OUTPUT
Z0 = 50
2.5 V
OUTPUT
RL = 50
5 pF
VT = 1.25 V
(a)
INCLUDING
JIG AND
SCOPE
R = 1667
R =1538
VDDQ
GND
10%
1 ns
ALL INPUT PULSES
90%
(b) (c)
90%
10%
1 ns
90%
10%
1 ns
Note
16. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 38-05524 Rev. *Q
Page 11 of 22
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| PDF Descargar | [ Datasheet CY7C1350G.PDF ] | |
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