|
|
PDF CY7C1441KVE33 Data sheet ( Hoja de datos )
| Número de pieza | CY7C1441KVE33 | |
| Descripción | 36-Mbit (1M x 36/2M x 18) Flow-Through SRAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de CY7C1441KVE33 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
CY7C1441KV33
CY7C1443KV33
CY7C1441KVE33
36-Mbit (1M × 36/2M × 18) Flow-Through
SRAM (With ECC)
36-Mbit (1M × 36/2M × 18) Flow-Through SRAM (With ECC)
Features
■ Supports 133-MHz bus operations
■ 1M × 36/2M × 18 common I/O
■ 3.3 V core power supply
■ 2.5 V or 3.3 V I/O power supply
■ Fast clock-to-output times
❐ 6.5 ns (133 MHz version)
■ Provide high-performance 2-1-1-1 access rate
■ User-selectable burst counter supporting Intel Pentium
interleaved or linear burst sequences
■ Separate processor and controller address strobes
■ Synchronous self-timed write
■ Asynchronous output enable
■ CY7C1441KV33, CY7C1443KV33, and CY7C1441KVE33 are
available in JEDEC-standard 100-pin TQFP and 165-ball
FBGA Pb-free packages.
■ IEEE 1149.1 JTAG-Compatible Boundary Scan
■ “ZZ” Sleep Mode option
■ On-chip error correction code (ECC) to reduce soft error rate
(SER)
Functional Description
The CY7C1441KV33/CY7C1443KV33/CY7C1441KVE33 are
3.3 V, 1M × 36/2M × 18/1M × 36 synchronous flow-through
SRAMs, respectively designed to interface with high-speed
microprocessors with minimum glue logic. Maximum access
delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip
counter captures the first address in a burst and increments the
address automatically for the rest of the burst access. All
synchronous inputs are gated by registers controlled by a
positive-edge-triggered Clock (CLK) input. The synchronous
inputs include all addresses, all data inputs, address-pipelining
Chip Enable (CE1), depth-expansion Chip Enables (CE2 and
CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write
Enables (BWx, and BWE), and Global Write (GW).
Asynchronous inputs include the Output Enable (OE) and the ZZ
pin.
The CY7C1441KV33/CY7C1443KV33/CY7C1441KVE33 allow
either interleaved or linear burst sequences, selected by the
MODE input pin. A HIGH selects an interleaved burst sequence,
while a LOW selects a linear burst sequence. Burst accesses
can be initiated with the Processor Address Strobe (ADSP) or the
cache Controller Address Strobe (ADSC) inputs. Address
advancement is controlled by the Address Advancement (ADV)
input.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or Address
Strobe Controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
Advance pin (ADV).
The CY7C1441KV33/CY7C1443KV33/CY7C1441KVE33
operate from a +3.3 V core power supply while all outputs may
operate with either a +2.5 V or +3.3 V supply. All inputs and
outputs are JEDEC-standard JESD8-5-compatible.
Selection Guide
Maximum access time
Maximum operating current
Description
× 18
× 36
133 MHz
6.5
150
170
Unit
ns
mA
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-66677 Rev. *H
• San Jose, CA 95134-1709 • 408-943-2600
Revised July 5, 2016
1 page  
Pin Configurations
Figure 1. 100-pin TQFP Pinout
CY7C1441KV33
CY7C1443KV33
CY7C1441KVE33
DQPC
DQC
DQC
VDDQ
VSSQ
DQC
DQC
DQC
DQC
VSSQ
VDDQ
DQC
DQC
NC
VDD
NC
VSS
DQD
DQD
VDDQ
VSSQ
DQD
DQD
DQD
DQD
VSSQ
VDDQ
DQD
DQD
DQPD
1 80
2 79
3 78
4 77
5 76
6 75
7 74
8 73
9 72
10 71
11 70
12 69
13 68
14 67
15
16
CY7C1441KV33/CY7C1441KVE33
66
65
17 (1M × 36) 64
18 63
19 62
20 61
21 60
22 59
23 58
24 57
25 56
26 55
27 54
28 53
29 52
30 51
DQPB
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
DQPA
NC
NC
NC
VDDQ
VSSQ
NC
NC
DQB
DQB
VSSQ
VDDQ
DQB
DQB
NC
VDD
NC
VSS
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQPB
NC
VSSQ
VDDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1443KV33
(2M × 18)
80 A
79 NC
78 NC
77 VDDQ
76 VSSQ
75 NC
74 DQPA
73 DQA
72 DQA
71 VSSQ
70 VDDQ
69 DQA
68 DQA
67 VSS
66 NC
65 VDD
64 ZZ
63 DQA
62 DQA
61 VDDQ
60 VSSQ
59 DQA
58 DQA
57 NC
56 NC
55 VSSQ
54 VDDQ
53 NC
52 NC
51 NC
Document Number: 001-66677 Rev. *H
Page 5 of 32
5 Page 
CY7C1441KV33
CY7C1443KV33
CY7C1441KVE33
Partial Truth Table for Read/Write
The partial truth table for read/write for CY7C1441KV33/CY7C1441KVE33 is as follows. [6, 7, 8]
Function (CY7C1441KV33/CY7C1441KVE33)
Read
Read
Write Byte A (DQA, DQPA)
Write Byte B (DQB, DQPB)
Write Bytes A, B (DQA, DQB, DQPA, DQPB)
Write Byte C (DQC, DQPC)
Write Bytes C, A (DQC, DQA, DQPC, DQPA)
Write Bytes C, B (DQC, DQB, DQPC, DQPB)
Write Bytes C, B, A (DQC, DQB, DQA, DQPC, DQPB,
DQPA)
Write Byte D (DQD, DQPD)
Write Bytes D, A (DQD, DQA, DQPD, DQPA)
Write Bytes D, B (DQD, DQA, DQPD, DQPA)
Write Bytes D, B, A (DQD, DQB, DQA, DQPD, DQPB,
DQPA)
Write Bytes D, B (DQD, DQB, DQPD, DQPB)
Write Bytes D, B, A (DQD, DQC, DQA, DQPD, DQPC,
DQPA)
Write Bytes D, C, A (DQD, DQB, DQA, DQPD, DQPB,
DQPA)
Write All Bytes
Write All Bytes
GW
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
BWE
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
BWD
X
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
X
BWC
X
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
X
BWB
X
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
X
BWA
X
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
X
Partial Truth Table for Read/Write
The partial truth table for read/write for CY7C1443KV33 is as follows. [6, 7, 8]
Function (CY7C1443KV33)
Read
Read
Write Byte A – (DQA and DQPA)
Write Byte B – (DQB and DQPB)
Write All Bytes
Write All Bytes
GW BWE
HH
HL
HL
HL
HL
LX
BWB
X
H
H
L
L
X
BWA
X
H
L
H
L
X
Notes
6. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
7. Table only lists a partial listing of the byte write combinations. Any Combination of BWX is valid Appropriate write is done based on which byte write is active.
8.
BWx represents any
enabled at the same
byte
time
wforriteansyiggniavel BnWwr[Ait.e.H. ].To
enable
any
byte
write
BWx,
a
Logic
LOW
signal
should
be
applied
at
clock
rise.Any
number
of
bye
writes
can
be
Document Number: 001-66677 Rev. *H
Page 11 of 32
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CY7C1441KVE33.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| CY7C1441KVE33 | 36-Mbit (1M x 36/2M x 18) Flow-Through SRAM | Cypress Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |