|
|
Número de pieza | CY7C1373KV33 | |
Descripción | 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM | |
Fabricantes | Cypress Semiconductor | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de CY7C1373KV33 (archivo pdf) en la parte inferior de esta página. Total 24 Páginas | ||
No Preview Available ! CY7C1371KV33
CY7C1371KVE33
CY7C1373KV33
18-Mbit (512K × 36/1M × 18) Flow-Through SRAM
with NoBL™ Architecture (With ECC)
18-Mbit (512K × 36/1M × 18) Flow-through SRAM with NoBL™ Architecture (With ECC)
Features
■ No Bus Latency (NoBL) architecture eliminates dead cycles
between write and read cycles
■ Supports up to 133-MHz bus operations with zero wait states
❐ Data is transferred on every clock
■ Pin-compatible and functionally equivalent to ZBT™ devices
■ Internally self-timed output buffer control to eliminate the need
to use OE
■ Registered inputs for flow through operation
■ Byte write capability
■ 3.3 V/2.5 V I/O power supply (VDDQ)
■ Fast clock-to-output times
❐ 6.5 ns (for 133-MHz device)
■ Clock enable (CEN) pin to enable clock and suspend operation
■ Synchronous self-timed writes
■ Asynchronous output enable
■ Available in JEDEC-standard Pb-free 100-pin TQFP packages
■ Three chip enables for simple depth expansion
■ Automatic power-down feature available using ZZ mode or CE
deselect
■ Burst capability – linear or interleaved burst order
■ Low standby power
■ On chip Error Correction Code (ECC) to reduce Soft Error Rate
(SER)
Functional Description
The CY7C1371KV33/CY7C1371KVE33/CY7C1373KV33 are
3.3 V, 512K × 36/1M × 18 synchronous flow through burst SRAM
designed specifically to support unlimited true back-to-back
read/write operations with no wait state insertion. The
CY7C1371KV33/CY7C1371KVE33/CY7C1373KV33
are
equipped with the advanced No Bus Latency (NoBL) logic
required to enable consecutive read/write operations with data
being transferred on every clock cycle. This feature dramatically
improves the throughput of data through the SRAM, especially
in systems that require frequent write-read transitions.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock input is qualified by the
clock enable (CEN) signal, which when deasserted suspends
operation and extends the previous clock cycle. Maximum
access delay from the clock rise is 6.5 ns (133-MHz device).
Write operations are controlled by the two or four byte write
select (BWX) and a write enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) provide for easy bank
selection and output tristate control. To avoid bus contention, the
output drivers are synchronously tristated during the data portion
of a write sequence.
Selection Guide
Maximum access time
Maximum operating current
Description
133 MHz 100 MHz Unit
6.5 8.5 ns
× 18 129
114 mA
× 36 149
134 mA
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-97852 Rev. *E
• San Jose, CA 95134-1709 • 408-943-2600
Revised July 1, 2016
1 page CY7C1371KV33
CY7C1371KVE33
CY7C1373KV33
Pin Configurations
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout
CY7C1371KV33/CY7C1371KVE33
BYTE C
BYTE D
DQPC
DQC
DQC
VDDQ
VSS
DQC
DQC
DQC
DQC
VSS
VDDQ
DQC
DQC
NC
VDD
NC
VSS
DQD
DQD
VDDQ
VSS
DQD
DQD
DQD
DQD
VSS
VDDQ
DQD
DQD
DQPD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80 DQPB
79 DQB
78 DQB
77 VDDQ
76 VSS
75
74
DQB
DQB
BYTE B
73 DQB
72 DQB
71 VSS
70 VDDQ
69 DQB
68 DQB
67 VSS
66 NC
65 VDD
64 ZZ
63 DQA
62 DQA
61 VDDQ
60 VSS
59 DQA
58 DQA
57
DQA
BYTE A
56 DQA
55 VSS
54 VDDQ
53 DQA
52 DQA
51 DQPA
Document Number: 001-97852 Rev. *E
Page 5 of 24
5 Page CY7C1371KV33
CY7C1371KVE33
CY7C1373KV33
Truth Table
The truth table for CY7C1371KV33/CY7C1371KVE33/CY7C1373KV33 are as follows. [1, 2, 3, 4, 5, 6, 7]
Operation
Deselect cycle
Deselect cycle
Deselect cycle
Continue deselect cycle
Read cycle (begin burst)
Read cycle (continue burst)
NOP/dummy read (begin burst)
Dummy read (continue burst)
Write cycle (begin burst)
Write cycle (continue burst)
NOP/write abort (begin burst)
Write abort (continue burst)
Ignore clock edge (stall)
Sleep mode
Address Used CE1 CE2 CE3 ZZ ADV/LD WE BWX OE CEN CLK
None
H X X L L X X X L L->H
DQ
Tristate
None
X X H L L X X X L L->H Tristate
None
X L X L L X X X L L->H Tristate
None
X X X L H X X X L L->H Tristate
External
L H LL
L H X L L L->H Data out (Q)
Next
X X X L H X X L L L->H Data out (Q)
External
L H LL
L H X H L L->H Tristate
Next
X X X L H X X H L L->H Tristate
External L H L L L L L X L L->H Data in (D)
Next
X X X L H X L X L L->H Data in (D)
None
L H L L L L H X L L->H Tristate
Next
X X X L H X H X L L->H Tristate
Current
X X X L X X X X H L->H
–
None
X X X H X X X X X X Tristate
Notes
1.
X=
are
“Don't Care.” H = Logic HIGH, L = Logic
asserted, see truth table for details.
LOW.
BWX
=
0
signifies
at
least
one
byte
write
select
is
active,
BWX
=
valid
signifies
that
the
desired
byte
write
selects
2. Write is defined by BWX, and WE. See Truth Table for read/write.
3. When a write cycle is detected, all I/Os are tristated, even during byte writes.
4. The DQs and DQPX pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. CEN = H, inserts wait states.
6. Device powers up deselected and the I/Os in a tristate condition, regardless of OE.
7.
OE is asynchronous and is not sampled with
or when the device is deselected, and DQs
the
and
clock rise. It is
DQPX = data
masked internally during
when OE is active.
write
cycles.
During
a
read
cycle
DQs
and
DQPX
=
tristate
when
OE
is
inactive
Document Number: 001-97852 Rev. *E
Page 11 of 24
11 Page |
Páginas | Total 24 Páginas | |
PDF Descargar | [ Datasheet CY7C1373KV33.PDF ] |
Número de pieza | Descripción | Fabricantes |
CY7C1373KV33 | 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM | Cypress Semiconductor |
Número de pieza | Descripción | Fabricantes |
SLA6805M | High Voltage 3 phase Motor Driver IC. |
Sanken |
SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
Analog Devices |
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |