PDF CY7C1471BV33 Data sheet ( Hoja de datos )

Número de pieza	CY7C1471BV33
Descripción	72-Mbit (2 M x 36/4 M x 18) Flow-Through SRAM
Fabricantes	Cypress Semiconductor
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No Preview Available ! CY7C1471BV33 CY7C1473BV33 72-Mbit (2 M × 36/4 M × 18) Flow-Through SRAM with NoBL™ Architecture 72-Mbit (2 M × 36/4 M × 18) Flow-Through SRAM with NoBL™ Architecture Features ■ No bus latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles ■ Supports up to 133 MHz bus operations with zero wait states ■ Data is transferred on every clock ■ Pin compatible and functionally equivalent to ZBT™ devices ■ Internally self timed output buffer control to eliminate the need to use OE ■ Registered inputs for flow through operation ■ Byte write capability ■ 3.3 V/2.5 V I/O supply (VDDQ) ■ Fast clock-to-output times ❐ 6.5 ns (for 133 MHz device) ■ Clock enable (CEN) pin to enable clock and suspend operation ■ Synchronous self-timed writes ■ Asynchronous output enable (OE) ■ CY7C1471BV33 available in JEDEC-standard Pb-free 100-pin thin quad flat pack (TQFP), Pb-free and non-Pb-free 165-ball fine-pitch ball grid array (FBGA) package. CY7C1473BV33 available in JEDEC-standard Pb-free 100-pin thin quad flat pack (TQFP) ■ Three chip enables (CE1, CE2, CE3) for simple depth expansion ■ Automatic power-down feature available using ZZ mode or CE deselect ■ IEEE 1149.1 JTAG boundary scan compatible ■ Burst capability – linear or interleaved burst order ■ Low standby power Functional Description The CY7C1471BV33 and CY7C1473BV33 are 3.3 V, 2 M × 36/4 M × 18 synchronous flow through burst SRAMs designed specifically to support unlimited true back-to-back read or write operations without the insertion of wait states. The CY7C1471BV33 and CY7C1473BV33 are equipped with the advanced No Bus Latency (NoBL) logic. NoBL™ is required to enable consecutive read or write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent write-read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is 6.5 ns (133 MHz device). Write operations are controlled by two or four Byte Write Select (BWX) and a Write Enable (WE) input. All writes are conducted with on-chip synchronous self timed write circuitry. Three synchronous chip enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output tri-state control. To avoid bus contention, the output drivers are synchronously tri-stated during the data portion of a write sequence. For a complete list of related documentation, click here. Selection Guide Maximum access time Maximum operating current Maximum CMOS standby current Description 133 MHz 6.5 305 120 Unit ns mA mA Cypress Semiconductor Corporation • 198 Champion Court Document Number: 001-15029 Rev. I • San Jose, CA 95134-1709 • 408-943-2600 Revised November 17, 2014 1 page Pin Configurations (continued) Figure 2. 100-pin TQFP (14 × 20 × 1.4 mm) pinout CY7C1473BV33 (4 M × 18) CY7C1471BV33 CY7C1473BV33 BYTE B NC NC NC VDDQ VSS NC NC DQB DQB VSS VDDQ DQB DQB NC VDD NC VSS DQB DQB VDDQ VSS DQB DQB DQPB NC VSS VDDQ NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 CY7C1473BV33 80 A 79 NC 78 NC 77 VDDQ 76 VSS 75 NC 74 DQPA 73 DQA 72 DQA 71 VSS 70 VDDQ 69 DQA 68 DQA 67 66 VSS NC BYTE A 65 VDD 64 ZZ 63 DQA 62 DQA 61 VDDQ 60 VSS 59 DQA 58 DQA 57 NC 56 NC 55 VSS 54 VDDQ 53 NC 52 NC 51 NC Document Number: 001-15029 Rev. I Page 5 of 32 5 Page CY7C1471BV33 CY7C1473BV33 Truth Table for Read/Write The read/write truth table for CY7C1471BV33 follows. [8, 9, 10] Function (CY7C1471BV33) Read Write – No bytes written Write byte A – (DQA and DQPA) Write byte B – (DQB and DQPB) Write byte C – (DQC and DQPC) Write byte D – (DQD and DQPD) Write all bytes Truth Table for Read/Write The read/write truth table for CY7C1473BV33 follows. [8, 9, 10] Function (CY7C1473BV33) Read Write – No bytes written Write byte a – (DQa and DQPa) Write byte b – (DQb and DQPb) Write both bytes WE BWa BWb BWc BWd HXXXX L HHHH L LHHH L H L HH L HH L H L HHH L LLLLL WE BWa HX LH LL LH LL BWb X H H L L Notes 8. X= are “Don't Care.” H = Logic HIGH, L = asserted, see section Truth Table LfoorgRiceLaOdW/W.rBiteWoXn=pLasgiegn1i1fiefosradteletaaislst.one Byte Write Select is active, BWX = Valid signifies that the desired Byte Write Selects 9. Write is defined by BWX, and WE. See section Truth Table for Read/Write on page 11. 10. Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write is based on which byte write is active. Document Number: 001-15029 Rev. *I Page 11 of 32 11 Page

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