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PDF CY7C1471BV25 Data sheet ( Hoja de datos )
| Número de pieza | CY7C1471BV25 | |
| Descripción | 72-Mbit (2 M x 36) Flow-Through SRAM | |
| Fabricantes | Cypress Semiconductor | |
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CY7C1471BV25
72-Mbit (2 M × 36)
Flow-Through SRAM with NoBL™ Architecture
72-Mbit (2 M × 36/1 M × 72) Flow-Through SRAM with NoBL™ Architecture
Features
■ No Bus Latency™ (NoBL™) architecture eliminates dead
cycles between write and read cycles
■ Supports up to 133 MHz bus operations with zero wait states
■ Data transfers on every clock
■ Pin compatible and functionally equivalent to ZBT™ devices
■ Internally self timed output buffer control to eliminate the need
to use OE
■ Registered inputs for flow through operation
■ Byte Write capability
■ 2.5-V I/O supply (VDDQ)
■ Fast clock-to-output times
❐ 6.5 ns (for 133-MHz device)
■ Clock Enable (CEN) pin to enable clock and suspend operation
■ Synchronous self timed writes
■ Asynchronous Output Enable (OE)
■ CY7C1471BV25 available in JEDEC-standard Pb-free 100-pin
TQFP package.
■ Three Chip Enables (CE1, CE2, CE3) for simple depth
expansion.
■ Automatic power down feature available using ZZ mode or CE
deselect.
■ Burst Capability – linear or interleaved burst order
■ Low standby power
Functional Description
The CY7C1471BV25, is 2.5 V, 2 M × 36 synchronous flow
through burst SRAMs designed specifically to support unlimited
true back-to-back read or write operations without the insertion
of wait states. The CY7C1471BV25, is equipped with the
advanced No Bus Latency (NoBL) logic required to enable
consecutive read or write operations with data transferred on
every clock cycle. This feature dramatically improves the
throughput of data through the SRAM, especially in systems that
require frequent write-read transitions.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock input is qualified by the
Clock Enable (CEN) signal, which when deasserted suspends
operation and extends the previous clock cycle. Maximum
access delay from the clock rise is 6.5 ns (133-MHz device).
Write operations are controlled by two or four Byte Write Select
(BWX) and a Write Enable (WE) input. All writes are conducted
with on-chip synchronous self timed write circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide easy bank selection
and output tristate control. To avoid bus contention, the output
drivers are synchronously tristated during the data portion of a
write sequence.
For a complete list of related documentation, click here.
Selection Guide
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Description
133 MHz
6.5
305
120
Unit
ns
mA
mA
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-15013 Rev. *N
• San Jose, CA 95134-1709 • 408-943-2600
Revised May 11, 2016
1 page  
CY7C1471BV25
Pin Definitions
Name
I/O
Description
A0, A1, A
BWA, BWB,
BWC, BWD
WE
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Address Inputs Used to Select One of the Address Locations. Sampled at the rising edge of the
CLK. A[1:0] are fed to the two-bit burst counter.
Byte Write Inputs, Active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the
rising edge of CLK.
Write Enable Input, Active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal
must be asserted LOW to initiate a write sequence.
ADV/LD
Input- Advance/Load Input. Used to advance the on-chip address counter or load a new address. When HIGH
Synchronous (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be
loaded into the device for an access. After being deselected, ADV/LD must be driven LOW to load a
new address.
CLK Input- Clock Input. Captures all synchronous inputs to the device. CLK is qualified with CEN. CLK is only
Clock recognized if CEN is active LOW.
CE1 Input- Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2
Synchronous and CE3 to select or deselect the device.
CE2 Input- Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1
Synchronous and CE3 to select or deselect the device.
CE3 Input- Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
Synchronous and CE2 to select or deselect the device.
OE Input- Output Enable, Asynchronous Input, Active LOW. Combined with the synchronous logic block inside
Asynchronous the device to control the direction of the I/O pins. When LOW, the I/O pins are enabled to behave as
outputs. When deasserted HIGH, I/O pins are tristated, and act as input data pins. OE is masked during
the data portion of a write sequence, during the first clock when emerging from a deselected state, when
the device has been deselected.
CEN
Input- Clock Enable Input, Active LOW. When asserted LOW the clock signal is recognized by the SRAM.
Synchronous When deasserted HIGH the clock signal is masked. Because deasserting CEN does not deselect the
device, CEN can be used to extend the previous cycle when required.
ZZ Input- ZZ “Sleep” Input. This active HIGH input places the device in a non-time-critical “sleep” condition with
Asynchronous data integrity preserved. For normal operation, this pin must be LOW or left floating. ZZ pin has an
internal pull down.
DQs I/O- Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered by the
Synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the
addresses presented during the previous clock rise of the read cycle. The direction of the pins is
controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX
are placed in a tristate condition.The outputs are automatically tristated during the data portion of a write
sequence, during the first clock when emerging from a deselected state, and when the device is
deselected, regardless of the state of OE.
DQPX
MODE
I/O- Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQs. During write
Synchronous sequences, DQPX is controlled by BWX correspondingly.
Input Strap Pin Mode Input. Selects the Burst Order of the Device.
When tied to Gnd selects linear burst sequence. When tied to VDD or left floating selects interleaved
burst sequence.
VDD
VDDQ
Power Supply Power Supply Inputs to the Core of the Device.
I/O Power Power Supply for the I/O Circuitry.
Supply
VSS Ground Ground for the Device.
NC – No Connects. Not internally connected to the die. 144M, 288M, 576M, and 1G are address expansion
pins and are not internally connected to the die.
Document Number: 001-15013 Rev. *N
Page 5 of 22
5 Page 
CY7C1471BV25
Capacitance
Parameter [14]
CADDRESS
CDATA
CCTRL
CCLK
CIO
Description
Address input capacitance
Data input capacitance
Control input capacitance
Clock input capacitance
Input-Output capacitance
Thermal Resistance
Parameter [14]
Description
JA Thermal resistance
(junction to ambient)
JC Thermal resistance
(junction to case)
Test Conditions
TA = 25°C, f = 1 MHz,
VDD = 2.5 V, VDDQ = 2.5 V
100-pin TQFP
Max
6
5
8
6
5
Unit
pF
pF
pF
pF
pF
Test Conditions
Test conditions follow standard test
methods and procedures for
measuring thermal impedance,
according to EIA/JESD51.
100-pin TQFP
Package
24.63
2.28
Unit
C/W
C/W
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms
2.5 V I/O Test Load
OUTPUT
Z0 = 50
2.5 V
OUTPUT
RL = 50
5 pF
VL = 1.25 V
(a)
INCLUDING
JIG AND
SCOPE
R = 1667
VDDQ
10%
GND
R = 1538
1 ns
ALL INPUT PULSES
90%
90%
10%
1 ns
(b) (c)
Note
14. Tested initially and after any design or process change that may affect these parameters.
Document Number: 001-15013 Rev. *N
Page 11 of 22
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet CY7C1471BV25.PDF ] | |
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