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PDF CY7C1474BV33 Data sheet ( Hoja de datos )
| Número de pieza | CY7C1474BV33 | |
| Descripción | 72-Mbit (2 M x 36/4 M x 18/1 M x 72) Pipelined SRAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY7C1470BV33
CY7C1472BV33
CY7C1474BV33
72-Mbit (2 M × 36/4 M × 18/1 M × 72)
Pipelined SRAM with NoBL™ Architecture
72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBL™ Architecture
Features
■ Pin-compatible and functionally equivalent to ZBT™
■ Supports 250 MHz bus operations with zero wait states
❐ Available speed grades are 250, 200, and 167 MHz
■ Internally self timed output buffer control to eliminate the need
to use asynchronous OE
■ Fully registered (inputs and outputs) for pipelined operation
■ Byte Write capability
■ Single 3.3 V power supply
■ 3.3 V/2.5 V I/O power supply
■ Fast clock-to-output time
❐ 3.0 ns (for 250 MHz device)
■ Clock Enable (CEN) pin to suspend operation
■ Synchronous self timed writes
■ CY7C1470BV33,
CY7C1472BV33
available
in
JEDEC-standard Pb-free 100-pin TQFP, Pb-free and
non-Pb-free 165-ball FBGA package. CY7C1474BV33
available in Pb-free and non-Pb-free 209-ball FBGA package
■ IEEE 1149.1 JTAG Boundary Scan compatible
■ Burst capability – linear or interleaved burst order
■ “ZZ” Sleep Mode option and Stop Clock option
Functional Description
The CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33
are 3.3 V, 2 M × 36/4 M × 18/1 M × 72 Synchronous pipelined
burst SRAMs with No Bus Latency™ (NoBL logic,
respectively. They are designed to support unlimited true
back-to-back read or write operations with no wait states. The
CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33 are
equipped with the advanced (NoBL) logic required to enable
consecutive read or write operations with data being transferred
on every clock cycle. This feature dramatically improves the
throughput of data in systems that require frequent read or write
transitions. The CY7C1470BV33, CY7C1472BV33, and
CY7C1474BV33 are pin compatible and functionally equivalent
to ZBT devices.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. The clock
input is qualified by the Clock Enable (CEN) signal, which when
deasserted suspends operation and extends the previous clock
cycle.
Write operations are controlled by the Byte Write Selects
(BWa–BWd for CY7C1470BV33, BWa–BWb for
CY7C1472BV33, and BWa–BWh for CY7C1474BV33) and a
Write Enable (WE) input. All writes are conducted with on-chip
synchronous self timed write circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. To avoid bus contention,
the output drivers are synchronously tri-stated during the data
portion of a write sequence.
For a complete list of related documentation, click here.
Selection Guide
Description
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
250 MHz
3.0
500
120
200 MHz
3.0
500
120
167 MHz
3.4
450
120
Unit
ns
mA
mA
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-15031 Rev. *M
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 20, 2014
1 page  
CY7C1470BV33
CY7C1472BV33
CY7C1474BV33
Pin Configurations
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout
DQPc
DQc
DQc
VDDQ
VSS
DQc
DQc
DQc
DQc
VSS
VDDQ
DQc
DQc
NC
VDD
NC
VSS
DQd
DQd
VDDQ
VSS
DQd
DQd
DQd
DQd
VSS
VDDQ
DQd
DQd
DQPd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1470BV33
(2 M × 36)
80 DQPb NC 1
79 DQb
NC 2
78 DQb
NC 3
77 VDDQ VDDQ 4
76 VSS
VSS 5
75 DQb NC 6
74 DQb
NC 7
73 DQb DQb 8
72 DQb DQb 9
71
70
VSS
VDDQ
VSS
VDDQ
10
11
69 DQb DQb 12
68
67
66
65
64
DQb
VSS
NC
VDD
ZZ
DQb
NC
VDD
NC
VSS
13
14
15
16
17
63 DQa DQb 18
62
61
60
DQa
VDDQ
VSS
DQb
VDDQ
VSS
19
20
21
59 DQa DQb 22
58 DQa DQb 23
57 DQa DQPb 24
56 DQa NC 25
55
54
VSS
VDDQ
VVDSDSQ
26
27
53 DQa NC 28
52 DQa NC 29
51 DQPa NC 30
CY7C1472BV33
(4 M × 18)
80 A
79 NC
78 NC
77 VDDQ
76 VSS
75 NC
74 DQPa
73 DQa
72 DQa
71 VSS
70 VDDQ
69 DQa
68 DQa
67 VSS
66 NC
65 VDD
64 ZZ
63 DQa
62 DQa
61 VDDQ
60 VSS
59 DQa
58 DQa
57 NC
56 NC
55 VSS
54 VDDQ
53 NC
52 NC
51 NC
Document Number: 001-15031 Rev. *M
Page 5 of 34
5 Page 
CY7C1470BV33
CY7C1472BV33
CY7C1474BV33
Truth Table
The truth table for CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33 follows. [1, 2, 3, 4, 5, 6, 7]
Operation
Deselect Cycle
Continue Deselect Cycle
Read Cycle (Begin Burst)
Read Cycle (Continue Burst)
NOP/Dummy Read (Begin Burst)
Dummy Read (Continue Burst)
Write Cycle (Begin Burst)
Write Cycle (Continue Burst)
NOP/Write Abort (Begin Burst)
Write Abort (Continue Burst)
Ignore Clock Edge (Stall)
Sleep Mode
Address Used CE ZZ ADV/LD WE BWx OE CEN CLK
None
H L L X X X L L–H
DQ
Tri-State
None
X L H X X X L L–H Tri-State
External
L L L H X L L L–H Data Out (Q)
Next
X L H X X L L L–H Data Out (Q)
External
L L L H X H L L–H Tri-State
Next
X L H X X H L L–H Tri-State
External
L L L L L X L L–H Data In (D)
Next
X L H X L X L L–H Data In (D)
None
L L L L H X L L–H Tri-State
Next
X L H X H X L L–H Tri-State
Current
X L X X X X H L–H
-
None
X H X X X X X X Tri-State
Notes
1. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BWx = 0 signifies at least one Byte Write Select is active, BWx = Valid
signifies that the desired byte write selects are asserted, see Partial Write Cycle Description on page 12 for details.
2. Write is defined by WE and BW[a:d]. See Partial Write Cycle Description on page 12 for details.
3. When a write cycle is detected, all IOs are tri-stated, even during Byte Writes.
4. The DQ and DQP pins are controlled by the current cycle and the OE signal.
5. CEN = H inserts wait states.
6. Device powers up deselected with the IOs in a tri-state condition, regardless of OE.
7.
OE is asynchronous
inactive or when the
and is
device
not sampled with the clock rise. It is
is deselected, and DQs= data when
masked internally
OE is active.
during
Write
cycles.
During
a
read
cycle
DQs
and
DQP[a:d]
=
tri-state
when
OE
is
Document Number: 001-15031 Rev. *M
Page 11 of 34
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CY7C1474BV33.PDF ] | |
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