PDF CY7C1461KV33 Data sheet ( Hoja de datos )

Número de pieza	CY7C1461KV33
Descripción	36-Mbit (1M x 36/2M x 18) Flow-Through SRAM
Fabricantes	Cypress Semiconductor
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No Preview Available ! CY7C1461KV33 CY7C1463KV33 36-Mbit (1M × 36/2M × 18) Flow-Through SRAM with NoBL™ Architecture 36-Mbit (1M × 36/2M × 18) Flow-Through SRAM with NoBL™ Architecture Features ■ No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles ■ Supports up to 133 MHz bus operations with zero wait states ❐ Data is transferred on every clock ■ Pin compatible and functionally equivalent to ZBT™ devices ■ Internally self timed output buffer control to eliminate the need to use OE ■ Registered inputs for flow through operation ■ Byte write capability ■ 3.3 V and 2.5 V I/O power supply ■ Fast clock-to-output times ❐ 6.5 ns (for 133-MHz device) ■ Clock Enable (CEN) pin to enable clock and suspend operation ■ Synchronous self timed writes ■ Asynchronous Output Enable ■ CY7C1461KV33, CY7C1463KV33 available JEDEC-standard Pb-free 100-pin TQFP packages in ■ Three chip enables for simple depth expansion ■ Automatic power down feature available using ZZ mode or CE deselect ■ Burst capability – linear or interleaved burst order ■ Low standby power Functional Description The CY7C1461KV33/CY7C1463KV33 are 3.3 V, 1M × 36/2M × 18 Synchronous Flow-Through Burst SRAMs designed specifically to support unlimited true back-to-back read and write operations without the insertion of wait states. The CY7C1461KV33/CY7C1463KV33 is equipped with the advanced NoBL logic required to enable consecutive read and write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent write-read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is 6.5 ns (133 MHz device). Write operations are controlled by the two or four Byte Write Select (BWX) and a Write Enable (WE) input. All writes are conducted with on-chip synchronous self timed write circuitry. Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output tri-state control. To avoid bus contention, the output drivers are synchronously tri-stated during the data portion of a write sequence. Selection Guide Maximum access time Maximum operating current Description 133 MHz Unit 6.5 ns × 18 150 mA × 36 170 Cypress Semiconductor Corporation • 198 Champion Court Document Number: 001-66681 Rev. G • San Jose, CA 95134-1709 • 408-943-2600 Revised June 7, 2016 1 page Pin Configurations Figure 1. 100-pin TQFP pinout CY7C1461KV33 CY7C1463KV33 BYTE C BYTE D DQPC DQC DQC VDDQ VSS DQC DQC DQC DQC VSS VDDQ DQC DQC NC VDD NC VSS DQD DQD VDDQ VSS DQD DQD DQD DQD VSS VDDQ DQD DQD DQPD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 CY7C1461KV33 80 DQPB 79 DQB 78 DQB 77 VDDQ 76 VSS 75 74 DQB DQB BYTE B 73 DQB 72 DQB 71 VSS 70 VDDQ 69 DQB 68 DQB 67 VSS 66 NC 65 VDD 64 ZZ 63 DQA 62 DQA 61 VDDQ 60 VSS 59 DQA 58 DQA 57 DQA BYTE A 56 DQA 55 VSS 54 VDDQ 53 DQA 52 DQA 51 DQPA Document Number: 001-66681 Rev. G Page 5 of 23 5 Page CY7C1461KV33 CY7C1463KV33 Partial Truth Table for Read/Write The partial truth table for read/write for CY7C1461KV33 is as follows. [8, 9] Function (CY7C1461KV33) Read Write – No Bytes Written Write Byte A – (DQA and DQPA) Write Byte B – (DQB and DQPB) Write Byte C – (DQC and DQPC) Write Byte D – (DQD and DQPD) Write All Bytes WE H L L L L L L Partial Truth Table for Read/Write The partial truth table for read/write for CY7C1463KV33 is as follows. [8, 9] Function (CY7C1463KV33) Read Write – No Bytes Written Write Byte a – (DQa and DQPa) Write Byte b – (DQb and DQPb) Write Both Bytes WE H L L L L BWA X H L H H H L BWB X H H L H H L BWC X H H H L H L BWD X H H H H L L BWb X H H L L BWa X H L H L Notes 8. X = “Don't Care.” H = logic HIGH, L = logic LOW. BWx = L signifies at least one byte write select is active, BWx = Valid signifies that the desired byte write selects are asserted, see truth table for details. 9. Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write is done based on which byte write is active. Document Number: 001-66681 Rev. *G Page 11 of 23 11 Page

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