PDF S4041-1B1 Data sheet ( Hoja de datos )

Número de pieza	S4041-1B1
Descripción	3.0V e.MMC Flash
Fabricantes	Cypress Semiconductor
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No Preview Available ! S4041-1B1 8 GB / 16 GB, 3.0 V e.MMC Flash Features ■ e.MMC 4.51 Specification compatible ❐ Backward compatible with previous e.MMC specifications ■ Storage temperature ❐ 40 °C to +85 °C ■ Operating voltage ❐ VCCQ: 1.7 V - 1.95 V or 2.7 V - 3.6 V ❐ VCC: 2.7 V - 3.6 V ■ Density: 8/16 GB of data storage ■ Data bus width: ❐ SDR mode: 1 bit, 4 bit, 8 bit ❐ DDR mode: 4 bit, 8 bit ❐ HS200 mode: 4 bit, 8 bit ■ Clock frequency: 52 MHz, 200 MHz (e.MMC 4.51) ❐ SDR mode: up to 52 MHz ❐ DDR mode: up to 52 MHz ❐ HS200 mode: up to 200 MHz ■ BGA packages ❐ 153-ball VFBGA: 13 mm  11.5 mm  1.0 mm ❐ 100-ball LBGA: 18 mm  14 mm  1.4 mm ■ Operating temperature range ❐ Embedded: 25 °C to +85 °C ❐ Industrial: 40 °C to +85 °C Key Supported Features ■ Boot Operation ■ Partition Management ■ Boot Area Partition ■ Replay Protected Memory Block (RPMB) ■ Sleep (CMD5) ■ Sanitize ■ Trim ■ High Priority Interrupt ■ Background Operations ■ Auto Background Operations ■ Hardware Reset ■ HS200 ■ Health Monitoring Performance ■ Sequential Read (MB/s): 120 ■ Sequential Write (MB/s): 20 ❐ Based on 16-GB device ❐ Bus in x8 I/O and HS200 modes ■ Random Read (IOPS): 5000 ■ Random Write (IOPS): 1400 Cypress Semiconductor Corporation • 198 Champion Court Document Number: 002-02760 Rev. H • San Jose, CA 95134-1709 • 408-943-2600 Revised March 03, 2016 1 page S4041-1B1 Table 1. Pin Description Pin Name Type DAT0 - DAT7 CMD CLK I/O I/O Input RST_N VCC VCCQ Input Power Power VDDI VSS VSSQ Power Power Power NC RFU — — Description Bidirectional data channels used for data transfers Bidirectional command channel used for device initialization and command transfers Clock input Hardware reset Supply voltage for the flash memory Supply voltage for the memory controller and MMC interface Internal power node. Connect capacitor to ground. Ground pin for the flash memory Ground pin for the memory controller and MMC interface Not connected Reserved for future use. Do not connect. Document Number: 002-02760 Rev. H Page 5 of 29 5 Page S4041-1B1 Card Specific Data Register Card Specific Data (CSD) Register contains the e.MMC access information. It includes data format, error correction, transfer speeds, and access times. It also includes information as to whether the DSR register can be accessed. Table 6. CSD Register Field Name Field ID CSD Structure CSD_STRUCTURE System Specification Version SPEC_VERS Reserved[5] — Data Read Access Time 1 TAAC Data Read Access Time 2 in CLK cycles (NSAC100) NSAC Maximum Bus Clock Frequency TRAN_SPEED Card Command Classes CCC Maximum Read Block Length READ_BL_LEN Partial Blocks For Read Allowed READ_BL_PARTIAL Write Block Misalignment WRITE_BLK_MISALIGN Read Block Misalignment READ_BLK_MISALIGN Dsr Implemented DSR_IMP Reserved[5] — Device Size C_SIZE Maximum Read Current at VDD min Maximum Read Current at VDD max Maximum Write Current at VDD min Maximum Write Current at VDD max Device Size Multiplier VDD_R_CURR_MIN VDD_R_CURR_MAX VDD_W_CURR_MIN VDD_W_CURR_MAX C_SIZE_MULT Erase Group Size ERASE_GRP_SIZE Erase Group Size Multiplier ERASE_GRP_MULT Size (Bits) 2 4 2 8 8 8 12 4 1 1 1 1 2 12 3 3 3 3 3 5 5 Write Protect Group Size WP_GRP_SIZE 5 Write Protect Group Enable Manufacturer Default Write Speed Factor Maximum Write Data Block Length Partial Blocks For Write Allowed Reserved[5] Content Protection Application File Format Group Copy Flag (OTP) Permanent Write Protection WP_GRP_ENABLE DEFAULT_ECC R2W_FACTOR WRITE_BL_LEN WRITE_BL_PARTIAL — CONTENT_PROT_APP FILE_FORMAT_GRP COPY PERM_WRITE_PROTECT 1 2 3 4 1 4 1 1 1 1 Cell Type R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R/W R/W R/W CSD Slice [127:126] [125:122] [121:120] [119:112] [111:104] [103:96] [95:84] [83:80] [79:79] [78:78] [77:77] [76:76] [75:74] [73:62] [61:59] [58:56] [55:53] [52:50] [49:47] [46:42] [41:37] [36:32] [31:31] [30:29] [28:26] [25:22] [21:21] [20:17] [16:16] [15:15] [14:14] [13:13] CSD Value 3h 4h — 4Fh 01h 32h 0F5h 9h 0h 0h 0h 0h — FFFh 7h 7h 7h 7h 7h 1Fh 1Fh 8 GB: 0Fh 16 GB: 1Fh 1h 0h 2h 9h 0h — 0h 0h 0h 0h Notes 5. Reserved bits should be read at ‘0’. 6. R = Read only. R/W = One time programmable and readable. R/W/E = Multiple writable with value kept after power failure, hardware reset assertion and any CMD0 reset and readable. 7. VDD represents the total consumed current for VCC and VCCQ. Document Number: 002-02760 Rev. *H Page 11 of 29 11 Page

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