FM31L276 Datasheet PDF - Cypress Semiconductor
Part Number | FM31L276 | |
Description | 64-Kbit/256-Kbit Integrated Processor Companion | |
Manufacturers | Cypress Semiconductor | |
Logo | ||
There is a preview and FM31L276 download ( pdf file ) link at the bottom of this page. Total 30 Pages |
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64-Kbit/256-Kbit Integrated Processor
Companion with F-RAM
256-Kbit (32 K × 8) Serial (SPI) F-RAM
Features
■ 64-Kbit/256-Kbit ferroelectric random access memory (F-RAM)
❐ Logically organized as 8 K × 8 (FM31L276) / 32 K × 8
(FM31L278)
❐ High-endurance 100 trillion (1014) read/writes
❐ 151-year data retention (See the Data Retention and
Endurance table)
❐ NoDelay™ writes
❐ Advanced high-reliability ferroelectric process
■ High Integration Device Replaces Multiple Parts
❐ Serial nonvolatile memory
❐ Real time clock (RTC)
❐ Low voltage reset
❐ Watchdog timer
❐ Early power-fail warning/NMI
❐ Two 16-bit event counter
❐ Serial number with write-lock for security
■ Real-time Clock/Calendar
❐ Backup current at 2 V: 1.15 A at +25 C
❐ Seconds through centuries in BCD format
❐ Tracks leap years through 2099
❐ Uses standard 32.768 kHz crystal (6 pF/12.5 pF)
❐ Software calibration
❐ Supports battery or capacitor backup
■ Processor Companion
❐ Active-low reset output for VDD and watchdog
❐ Programmable low-VDD reset trip point
❐ Manual reset filtered and debounced
❐ Programmable watchdog timer
❐ Dual Battery-backed event counter tracks system intrusions
or other events
❐ Comparator for power-fail interrupt
❐ 64-bit programmable serial number with lock
■ Fast 2-wire serial interface (I2C)
❐ Up to 1-MHz frequency
❐ Supports legacy timings for 100 kHz and 400 kHz
❐ RTC, Supervisor controlled via I2C interface
❐ Device select pins for up to 4 memory devices
■ Low power consumption
❐ 1.5 mA active current at 1 MHz
❐ 120 A standby current
■ Operating voltage: VDD = 2.7 V to 3.6 V
■ Industrial temperature: –40 C to +85 C
■ 14-pin small outline integrated circuit (SOIC) package
■ Restriction of hazardous substances (RoHS) compliant
■ Underwriters laboratory (UL) recognized
Functional Overview
The FM31L276/FM31L278 device integrates F-RAM memory
with the most commonly needed functions for processor-based
systems. Major features include nonvolatile memory, real time
clock, low-VDD reset, watchdog timer, nonvolatile event counter,
lockable 64-bit serial number area, and general purpose
comparator that can be used for a power-fail (NMI) interrupt or
any other purpose.
The FM31L276/FM31L278 is a 64-Kbit/256-Kbit nonvolatile
memory employing an advanced ferroelectric process. A
ferroelectric random access memory or F-RAM is nonvolatile
and performs reads and writes similar to a RAM. This memory is
truly nonvolatile rather than battery backed. It provides reliable
data retention for 151 years while eliminating the complexities,
overhead, and system-level reliability problems caused by other
nonvolatile memories. The FM31L276/FM31L278 is capable of
supporting 1014 read/write cycles, or 100 million times more write
cycles than EEPROM.
The real time clock (RTC) provides time and date information in
BCD format. It can be permanently powered from an external
backup voltage source, either a battery or a capacitor. The
timekeeper uses a common external 32.768 kHz crystal and
provides a calibration mode that allows software adjustment of
timekeeping accuracy.
The processor companion includes commonly needed CPU
support functions. Supervisory functions include a reset output
signal controlled by either a low VDD condition or a watchdog
timeout. RST goes active when VDD drops below a
programmable threshold and remains active for 100 ms after
VDD rises above the trip point. A programmable watchdog timer
runs from 100 ms to 3 seconds. The watchdog timer is optional,
but if enabled it will assert the reset signal for 100 ms if not
restarted by the host before the timeout. A flag-bit indicates the
source of the reset.
A comparator on PFI compares an external input pin to the
onboard 1.2 V reference. This is useful for generating a
power-fail interrupt (NMI) but can be used for any purpose. The
family also includes a programmable 64-bit serial number that
can be locked making it unalterable. Additionally it offers a dual
battery-backed event counter that tracks the number of rising or
falling edges detected on a dedicated input pin.
For a complete list of related documentation, click here.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-86392 Rev. *B
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 5, 2014
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FM31L276/FM31L278
Overview
The FM31L276/FM31L278 device combines a serial nonvolatile
RAM with a real time clock (RTC) and a processor companion.
The companion is a highly integrated peripheral including a
processor supervisor, a comparator used for early power-fail
warning, nonvolatile event counters, and a 64-bit serial number.
The FM31L276/FM31L278 integrates these complementary but
distinct functions under a common interface in a single package.
The product is organized as two logical devices. The first is a
memory and the second is the companion which includes all the
remaining functions. From the system perspective they appear
to be two separate devices with unique IDs on the serial bus.
The memory is organized as a standalone nonvolatile I2C
memory using standard device ID value. The real time clock and
supervisor functions are accessed with a separate I2C device ID.
This allows clock/calendar data to be read while maintaining the
most recently used memory address. The clock and supervisor
functions are controlled by 25 special function registers. The
RTC and event counter circuits are maintained by the power
source on the VBAK pin, allowing them to operate from battery or
backup capacitor power when VDD drops below a set threshold.
Each functional block is described below.
Memory Architecture
The FM31L276/FM31L278 device is available in memory size
64-Kbit/256-Kbit. The device uses two-byte addressing for the
memory portion of the chip. This makes the device software
compatible with its standalone memory counterparts, but makes
them compatible within the entire family.
The memory array is logically organized as 8,192 × 8 bits /
32,768 × 8 bits and is accessed using an industry-standard I2C
interface. The memory is based on F-RAM technology.
Therefore it can be treated as RAM and is read or written at the
speed of the I2C bus with no delays for write operations. It also
offers effectively unlimited write endurance unlike other
nonvolatile memory technologies. The I2C protocol is described
on page 19.
The memory array can be write-protected by software. Two bits
in the processor companion area (WP1, WP0 in register 0Bh)
control the protection setting. Based on the setting, the protected
addresses cannot be written and the I2C interface will not
acknowledge any data to protected addresses. The special
function registers containing these bits are described in detail
below.
Table 1. Block Memory Write Protection
WP1
0
0
1
1
WP0
0
1
0
1
Protected Address Range
None
Bottom 1/4
Bottom 1/2
Full array
Processor Companion
In addition to nonvolatile RAM, the FM31L276/FM31L278
incorporates a real time clock and highly integrated processor
companion. The companion includes a low-VDD reset, a
programmable watchdog timer, a battery-backed event
counters, a comparator for early power-fail detection or other
purposes, and a 64-bit serial number.
Processor Supervisor
Supervisors provide a host processor two basic functions:
detection of power supply fault conditions and a watchdog timer
to escape a software lockup condition. The
FM31L276/FM31L278 has a reset pin (RST) to drive a processor
reset input during power faults, power-up, and software lockups.
It is an open drain output with a weak internal pull-up to VDD. This
allows other reset sources to be wire-OR'd to the RST pin. When
VDD is above the programmed trip point, RST output is pulled
weakly to VDD. If VDD drops below the reset trip point voltage
level (VTP), the RST pin will be driven LOW. It will remain LOW
until VDD falls too low for circuit operation which is the VRST level.
When VDD rises again above VTP, RST continues to drive LOW
for at least 100 ms (tRPU) to ensure a robust system reset at a
reliable VDD level. After tRPU has been met, the RST pin will
return to the weak HIGH state. While RST is asserted, serial bus
activity is locked out even if a transaction occurred as VDD
dropped below VTP. A memory operation started while VDD is
above VTP will be completed internally.
Table 1 below shows how bit VTP controls the trip point of the
low-VDD reset. They are located in register 0Bh, bits 1 and 0. The
reset pin will drive LOW when VDD is below the selected VTP
voltage, and the I2C interface and F-RAM array will be locked
out. Note that the bit 1 location is a don't care. Figure 2 illustrates
the reset operation in response to a low VDD.
Table 2. VTP setting
VTP Setting
2.6 V
2.9 V
VTP
0
1
Figure 2. Low VDD Reset
VDD
VTP
tRPU
RST
A watchdog timer can also be used to drive an active reset signal.
The watchdog is a free-running programmable timer. The
timeout period can be software programmed from 100 ms to 3
seconds in 100 ms increments via a 5-bit nonvolatile register. All
programmed settings are minimum values and vary with
Document Number: 001-86392 Rev. *B
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