CY14V116G7 Datasheet PDF - Cypress Semiconductor
| Part Number | CY14V116G7 | |
| Description | 16-Mbit nvSRAM | |
| Manufacturers | Cypress Semiconductor | |
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CY14V116F7
CY14V116G7
16-Mbit nvSRAM with Asynchronous
NAND Interface
16-Mbit nvSRAM with Asynchronous NAND Interface
Features
■ 16-Mbit nonvolatile static random access memory (nvSRAM)
❐ Performance up to 33 MT/s per I/O
❐ Maximum data throughput using ×16 bus – 528 Mbps
❐ Industry-standard asynchronous NAND Flash interface with
reduced instruction set
❐ Shared address, data, and command bus
• Address and command bus is 8 bits
• Command is sent in one or two command cycles
• Address is sent in five address cycles
• Data bus width is ×8 or ×16 bits
■ Modes of operation:
❐ Asynchronous NAND Interface I/O with 30-ns access time
❐ Status Register with a software method for detecting the fol-
lowing:
• Nonvolatile STORE completion
• Pass/Fail condition of previous command
• Write protect status
■ Hands-off automatic STORE on power-down with only a small
capacitor
■ STORE to QuantumTrap nonvolatile elements is initiated by a
software command, a dedicated hardware pin, or AutoStore on
power-down
■ RECALL to SRAM initiated by software or power-up
■ High reliability
❐ Infinite read, write, and RECALL cycles
❐ 1 million STORE cycles to QuantumTrap
■ Data retention: 20 years at 85 C
■ Operating voltage
❐ Core VCC = 2.7 V to 3.6 V; I/O VCCQ = 1.70 V to 1.95 V
■ 165-ball fine-pitch ball grid array (FBGA) package
■ Industrial temperature: –40 C to +85 C
■ Restriction of hazardous substances (RoHS) compliant
Overview
Cypress nvSRAM combines high-performance SRAM cells with
nonvolatile elements in a monolithic integrated circuit. The
embedded nonvolatile elements incorporate the
Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) technology,
producing the world's most reliable nonvolatile memory. The
SRAM can be read and written an infinite number of times. The
nonvolatile data resides in the nonvolatile elements and does not
change when data is written to the SRAM.
The CY14V116F7/CY14V116G7 nvSRAM provides access
through a standard asynchronous NAND interface and supports
the ×8 and ×16 interface options. In the case of ×16 interface,
data bytes are transmitted over the DQ[15:0] lines and has
double the throughput compared to the DQ[7:0] bus. The
CY14V116F7/ CY14V116G7 uses a highly multiplexed DQ bus
to transfer data, addresses, and instructions. All addresses and
commands are always transmitted over the data bus DQ[7:0].
Therefore, in the case of the ×16 bus interface, the upper eight
data bits DQ[15:8] become don’t care bits during the address and
command cycles. The CY14V116F7/CY14V116G7 uses five
control pins (CLE, ALE, CE, RE, and WE) to transfer command,
address, and data during read and write operations. Additional
I/O pins, such as write protect (WP), ready/busy (R/B), and HSB
STORE, are used to support features in the device.
The asynchronous NAND interface nvSRAM is aligned to a
majority of the ONFI 1.0 specifications and supports data access
speed up to 33 MHz.
For a complete list of related documentation, click here.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-75528 Rev. *J
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 7, 2015
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CY14V116F7
CY14V116G7
Pin Definitions
Pin Name I/O Type
Description
Ready/Busy. The ready/busy signal indicates the device status. When it is pulled LOW, the signal
R/B
Output
indicates that nvSRAM is busy doing either a STORE or a power-up RECALL or a Software
RECALL/Software STORE/AutoStore Disable/AutoStore Enable operation. This signal is an open drain
output and requires an external pull-up resistor.
RE Input Read Enable. The read enable signal enables the data output during read operation.
CE
Input
Chip Enable. The chip enable signal selects the device when pulled LOW. When chip enable is HIGH
and the device is not busy doing a STORE operation, the device goes into a low-power standby state.
CLE
Input
Command Latch Enable. The command latch enable signal is used to latch the command byte. This
is one of the signals used by the host to indicate the type of bus cycle (command, address, and data).
ALE
Input
Address Latch Enable. The address latch enable signal is used to latch the address byte. This is one
of the signals used by the host to indicate the type of bus cycle (command, address, and data).
WE Input Write Enable. The write enable signal controls the latching of the input data on every rising edge.
WP Input Write Protect. The WP disables the SRAM write operation in nvSRAM if pulled LOW.
DQ[7:0][1]
Input/Output
I/O Port, 8 bits for the ×8 configuration. The I/O port is an 8-bit wide bidirectional port for transferring
address, command, and data to and from the device.
I/O Port, 16 bits for the ×16 configuration. The I/O port is a 16-bit wide bidirectional bus to transfer
DQ[15:0][1] Input/Output data words to and from the device during write and read operations. Address and commands are always
transmitted over the lower 8 bits DQ[7:0].
HSB
Input Hardware STORE. When pulled LOW external to the chip, it will initiate a nonvolatile STORE operation.
VCAP
Power supply
AutoStore capacitor: Supplies power to the nvSRAM during power loss to store data from SRAM to
nonvolatile elements.
VCC
VCCQ
VSS
R
Power supply Power. Power supply inputs to the core of the device.
Power supply I/O Power. Power supply inputs for the inputs and outputs of the device.
Power supply Ground for the device. Must be connected to ground of the system.
R Reserved. These pins are reserved, should be left unconnected by the host.
NC NC No Connect. Die pads are not connected to the package pin.
Discovery and Initialization
When the power-up cycle starts and VCC crosses the VSWITCH
threshold, the device initializes an internal Power-up RECALL
operation and pulls the R/B pin LOW for tRECALL duration. When
the power-up cycle is completed, the device releases the R/B
pin, which is then pulled HIGH by an external pull-up resistor
connected to it. The R/B HIGH indicates the device’s ready
status and allows the host controller to communicate with the
device by executing opcodes. All supported opcodes are
described in Table 3 on page 9.
nvSRAM Bus Operations
The nvSRAM device I/Os are multiplexed. Data I/O, addresses,
and commands all share the same I/O pins. DQ[15:8] are used
only for data in the ×16 configuration. Addresses and commands
are always transmitted through DQ[7:0] and data through
DQ[15:0] in the ×16 configuration.
The command sequence normally consists of a Command Latch
cycle, Address Input cycles, and one or more Data cycles, either
Read or Write.
Control Signals
The nvSRAM control signals, such as CE, WE, RE, CLE, ALE,
and WP, control the nvSRAM device read and write operations.
The CE is used to enable the device when pulled LOW and the
device is not in the busy state. When the nvSRAM is selected, it
accepts command, address, and data bytes. The nvSRAM will
enter the standby mode if CE goes HIGH while data is being
transferred and the device is not busy.
A HIGH CLE signal, along with CE and WE LOW, indicates a
command input cycle. Similarly, a HIGH ALE signal, along with
CE and WE LOW, indicates an Address Input cycle.
Note
1. Data DQ[7:0] for the ×8 configuration and data DQ[15:0] for the ×16 configuration.
Document Number: 001-75528 Rev. *J
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