ZSSC1751 Datasheet PDF - IDT
| Part Number | ZSSC1751 | |
| Description | Data Acquisition System Basis Chip | |
| Manufacturers | IDT | |
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Data Acquisition
System Basis Chip
ZSSC1750 / ZSSC1751
Datasheet
Brief Description
The ZSSC1750 and ZSSC1751 are System Basis
Chips (SBCs) with a dual-channel ADC for battery
sensing/management in automotive, industrial, and
medical systems. The ZSSC1750 and ZSSC1751
feature an SPI interface; in addition, the ZSSC1750
has an integrated LIN 2.1 transceiver.
One of the two input channels measures the battery
current IBAT via the voltage drop at the external shunt
resistor. The second channel measures the battery
voltage VBAT and the temperature.
By simultaneously measuring VBAT and IBAT, it is
possible to determine dynamically the internal
resistance of the battery, Rdi, which is correlated
with the state-of-health (SOH) of the battery. By
integrating IBAT, it is possible to determine the state-
of-charge (SOC) and the state-of-function (SOF) of
the battery.
During Sleep Mode, the system makes periodic
measurements to monitor the discharge of the
battery. Measurement cycles are controlled by user
software and include various wake-up conditions.
The ZSSC1750/51 is optimized for ultra-low power
consumption drawing only 60µA or less in this mode.
Features
• Two high-precision 24-bit sigma-delta ADCs
(18-bit with no missing codes);
sample rate: 1Hz to 16kHz
• On-chip voltage reference (5ppm/K typical)
• Current channel
IBAT offset error: ≤ 10mA
IBAT resolution: ≤ 1mA
Programmable gain: 4 to 512
Max. differential input stage input range: ±300mV
• Voltage channel
Input range: 4 to 28.8V
Voltage accuracy: ±60ppm FSR* = 1.73mV
• Temperature channel
External temperature sensor (NTC)
Factory-calibrated internal temp. sensor: ±2°C
• LIN 2.1/SAE J2602-1 transceiver (ZSSC1750 only)
• Typical current consumption
Normal Mode: 12mA
Sleep Mode: ≤ 60µA
Benefits
• Integrated, precision measurement solution for
accurate prediction of battery state of health
(SOH), state of charge (SOC), or state of
function (SOF)
• Robust power-on-reset (POR) concept for harsh
automotive environments
• On-chip precision oscillator accuracy: ±1%
• On-chip low-power oscillator
• Only a few external components needed
• Easy communication via SPI interface
• Power supply, interrupt, and reset signals for
external microcontroller
• Watchdog timer with dedicated oscillator
• Industry’s smallest footprint allows minimal
module size and cost
• AEC-Q100 qualified solution
Available Support
• Evaluation Kit
• Application Notes
Physical Characteristics
• Operation temperature up to -40°C to +125°C
• Supply voltage: 4.2 to 18V
• Small footprint package: PQFN36 6x6 mm
* FSR = full-scale range.
Basic ZSSC1750/51 Application Circuit
+ -To Harness
Car Chassis Ground
Rshunt
+-
Battery
VBAT
VDDE
VDDP 3.3V, <30mA
LIN-I/F
LIN (ZSSC1750 )
INP
INN
VDDA
RX
TX
IRQN
MCU_RSTN
MCU_CLK
NTH
NTC ZSSC1750/51
NTL SPI
VSSA VSSE
VDD
IRQ Interface
RST
to Host
CLK (opt.) (e.g. CAN)
I/F
µC
SPI
VSS
© 2016 Integrated Device Technology, Inc.
1
April 20, 2016
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ZSSC1750 / ZSSC1751 Datasheet
Figure 3.7 LP/ULP State Performing Current, Voltage, and Temperature Measurements
with discCvtCnt == 2..................................................................................................................... 56
Figure 3.8 LP/ULP State Performing Current, Voltage, and Temperature Measurements
with discCvtCnt == 5..................................................................................................................... 56
Figure 3.9 LP/ULP State Performing Current, Voltage, and Temperature Measurements
with discCvtCnt == 1..................................................................................................................... 57
Figure 3.10 LP/ULP State Performing Continuous Current-Only Measurements ............................................... 58
Figure 3.11 Performing Continuous Current and Voltage Measurements during LP/ULP State......................... 60
Figure 3.12 Functional Block Diagram of the Analog Measurement Subsystem ................................................ 64
Figure 3.13 FP ADC Clocking Scheme for sdmPos = sdmPos2 = 2; sdmClkDivFp = 1;
sdmChopClkDiv = 0........................................................................................................................ 66
Figure 3.14 FP ADC Clocking for sdmPos = 1 and sdmPos2 = 4; sdmClkDivFp = 1; sdmChopClkDiv = 0... 66
Figure 3.15 FP ADC Clocking for sdmPos = 3 and sdmPos2 = 0; sdmClkDivFp = 1; sdmChopClkDiv = 0... 67
Figure 3.16 FP ADC Clocking for sdmPos = 0 and sdmPos2 = 3; sdmClkDivFp = 1; sdmChopClkDiv = 0... 67
Figure 3.17 LP/ULP ADC Clocking Scheme; sdmClkDivLp = 5; sdmChopClkDiv = 0 ................................... 68
Figure 3.18 Functional Block Diagram of the Digital ADC Data Path .................................................................. 69
Figure 3.19 Data Post Correction ........................................................................................................................ 70
Figure 3.20 Data Representation through Data Post Correction including Over-Range and Overflow Levels ... 71
Figure 3.21 Common Enable for the “set overrange” and “set overflow” Interrupt Strobes for Current .............. 72
Figure 3.22 Individual SRCS................................................................................................................................ 87
Figure 3.23 Individual MRCS (Example for Result Counter of 3) ........................................................................ 87
Figure 3.24 Continuous SRCS............................................................................................................................. 88
Figure 3.25 Continuous MRCS (Example for Result Counter of 3) ..................................................................... 88
Figure 3.26 Stopping Continuous SRCS ............................................................................................................. 89
Figure 3.27 Stopping Continuous MRCS (Example for Result Counter of 3)...................................................... 89
Figure 3.28 Interrupting a Continuous SRCS ...................................................................................................... 90
Figure 3.29 Interrupting a Continuous MRCS (Example for Result Counter of 3)............................................... 90
Figure 3.30 Signal Behavior of adcMode ............................................................................................................ 91
Figure 3.31 Timing for Current, Voltage, and Internal Temperature Measurements without Chopping for
Different Configurations of the Average Filter .................................................................................. 93
Figure 3.32 Timing for External Temperature Measurements without Chopping when
No Average Filter is Enabled ............................................................................................................ 94
Figure 3.33 Timing for Current, Voltage, and Internal Temperature Measurements using Chopping................. 95
Figure 3.34 Timing for External Temperature Measurements using Chopping................................................... 96
Figure 3.35 Usage of Register adcCaccTh for the Digital ADC BIST ................................................................ 98
Figure 3.36 Bit Stream of ADC Interface Test at STO Pad ................................................................................. 99
Figure 3.37 Protection Logic of the LIN TXD Line ............................................................................................. 100
Figure 3.38 Waveform Showing the Gating Principle for Non-zero Values of linShortDelay...................... 101
Figure 4.1 Optional External Components for ZSSC1750............................................................................... 111
Figure 4.2 Optional External Components for ZSSC1751............................................................................... 111
Figure 5.1 ZSSC1750/51 PQFN36 6x6mm Package Pin-out (Top View) ....................................................... 112
Figure 5.2 Package Drawing of the ZSSC1750/51 .......................................................................................... 114
© 2016 Integrated Device Technology, Inc.
5
April 20, 2016
Preview 5 Page |
Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for ZSSC1751 electronic component. |
| Information | Total 30 Pages | |
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| Download | [ ZSSC1751.PDF Datasheet ] | |
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