PDF CY2XP311 Data sheet ( Hoja de datos )

Número de pieza	CY2XP311
Descripción	312.5 MHz LVPECL Clock Generator
Fabricantes	Cypress Semiconductor
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No Preview Available ! CY2XP311 312.5 MHz LVPECL Clock Generator 312.5 MHz LVPECL Clock Generator Features ■ One LVPECL output pair ■ Output frequency: 312.5 MHz ■ External crystal frequency: 25 MHz ■ Low RMS phase jitter at 312.5 MHz, using 25-MHz crystal (1.875 MHz to 20 MHz): 0.3 ps (typical) ■ Pb-free 8-pin TSSOP package ■ Supply voltage: 3.3 V or 2.5 V ■ Commercial and industrial temperature ranges Functional Description The CY2XP311 is a PLL (phase locked loop) based high performance clock generator. It is optimized to generate 10 GB Ethernet, SONET, and other high performance clock frequencies. It also produces an output frequency that is 12.5 times the crystal frequency. It uses Cypress’s low noise VCO technology to achieve 0.3 ps typical RMS phase jitter, which meets both 10 GB Ethernet and SONET jitter requirements. The CY2XP311 has a crystal oscillator interface input and one LVPECL output pair. For a complete list of related documentation, click here. Logic Block Diagram External Crystal XIN CRYSTAL OSCILLATOR XOUT OE PHASE DETECTOR VCO /25 /2 CLK CLK# Cypress Semiconductor Corporation • 198 Champion Court Document Number: 001-59931 Rev. D • San Jose, CA 95134-1709 • 408-943-2600 Revised November 20, 2014 1 page CY2XP311 DC Electrical Characteristics Parameter IDD IDDT VOH VOL VOD1 VOD2 VOCM IOZ VIH VIL IIH IIL CIN[3] CINX[3] Description Test Conditions Operating supply current with output unterminated VDD = 3.465 V, OE = VDD, output unterminated VDD = 2.625 V, OE = VDD, output unterminated Operating supply current with output terminated VDD = 3.465 V, OE = VDD, output terminated VDD = 2.625 V, OE = VDD, output terminated LVPECL output high voltage LVPECL output low voltage LVPECL peak-to-peak output voltage swing LVPECL output voltage swing (VOH – VOL) LVPECL output common mode voltage (VOH + VOL)/2 LVPECL output leakage current Input high voltage, OE Pin VDD = 3.3 V or 2.5 V, RTERM = 50  to VDD – 2.0 V VDD = 3.3 V or 2.5 V, RTERM = 50  to VDD – 2.0 V VDD = 3.3 V or 2.5 V, RTERM = 50  to VDD – 2.0 V VDD = 2.5 V, RTERM = 50  to VDD – 1.5 V VDD = 2.5 V, RTERM = 50  to VDD – 1.5 V Output off, OE = VSS – Input low voltage, OE Pin – Input high current, OE Pin Input low current, OE Pin Input capacitance, OE Pin OE = VDD OE = VSS – Pin capacitance, XIN & XOUT – Min Typ Max Unit – – 125 mA – – 120 mA – – 150 mA – – 145 mA VDD – 1.15 VDD – 2.0 600 – VDD – 0.75 V – VDD – 1.625 V – 1000 mV 500 – 1000 mV 1.2 – –V –35 – 35 A 0.7 × VDD – VDD + 0.3 V –0.3 – 0.3 × VDD V – – 115 µA –50 – – µA – 15 – pF – 4.5 – pF Notes 3. Not 100% tested, guaranteed by design and characterization. Document Number: 001-59931 Rev. D Page 5 of 14 5 Page CY2XP311 Package Drawing and Dimensions Figure 13. 8-pin TSSOP (4.40 mm Body) Package Outline, 51-85093 51-85093 E Document Number: 001-59931 Rev. D Page 11 of 14 11 Page

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Número de pieza	Descripción	Fabricantes
CY2XP31	312.5 MHz LVPECL Clock Generator	Cypress Semiconductor
CY2XP311	312.5 MHz LVPECL Clock Generator	Cypress Semiconductor

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