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PDF CS2000-CP Data sheet ( Hoja de datos )
| Número de pieza | CS2000-CP | |
| Descripción | Fractional-N Clock Synthesizer & Clock Multiplier | |
| Fabricantes | Cirrus Logic | |
| Logotipo |  |
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CS2000-CP
Fractional-N Clock Synthesizer & Clock Multiplier
Features
Delta-Sigma Fractional-N Frequency Synthesis
– Generates a Low Jitter 6 - 75 MHz Clock
from an 8 - 75 MHz Reference Clock
Clock Multiplier / Jitter Reduction
– Generates a Low Jitter 6 - 75 MHz Clock
from a Jittery or Intermittent 50 Hz to
30 MHz Clock Source
Highly Accurate PLL Multiplication Factor
– Maximum Error Less Than 1 PPM in High-
Resolution Mode
I²C / SPI™ Control Port
Configurable Auxiliary Output
Flexible Sourcing of Reference Clock
– External Oscillator or Clock Source
– Supports Inexpensive Local Crystal
Minimal Board Space Required
– No External Analog Loop-filter
Components
The CS2000-CP is an extremely versatile system
clocking device that utilizes a programmable phase
lock loop. The CS2000-CP is based on a hybrid ana-
log-digital PLL architecture comprised of a unique
combination of a Delta-Sigma Fractional-N Frequency
Synthesizer and a Digital PLL. This architecture allows
for both frequency synthesis/clock generation from a
stable reference clock as well as generation of a low-
jitter clock relative to an external noisy synchronization
clock. The design is also unique in that it can generate
low-jitter clocks relative to noisy external synchroniza-
tion clocks at frequencies as low as 50 Hz. The
CS2000-CP supports both I²C and SPI for full software
control.
The CS2000-CP is available in a 10-pin MSOP
package in Commercial (-10°C to +70°C), Automotive-
D (-40°C to +85°C), and Automotive-E (-40°C to
+105°C) grades. Customer development kits are also
available for device evaluation. Please see “Ordering
Information” on page 36 for complete details.
I²C/SPI
Software Control
I²C / SPI
3.3 V
Timing Reference
Frequency Reference
PLL Output
Lock Indicator
Auxiliary
Output
8 MHz to 75 MHz
Low-Jitter Timing
Reference
50 Hz to 30 MHz
Frequency
Reference
http://www.cirrus.com
Fractional-N
Frequency Synthesizer
Output to Input
Clock Ratio
N
Digital PLL & Fractional
N Logic
Output to Input
Clock Ratio
Copyright Cirrus Logic, Inc. 2009–2015
(All Rights Reserved)
6 to 75 MHz
PLL Output
SEPT '15
DS761F3
1 page  
1. PIN DESCRIPTION
CS2000-CP
VD
GND
CLK_OUT
AUX_OUT
CLK_IN
1
2
3
4
5
10 SDA/CDIN
9 SCL/CCLK
8 AD0/CS
7 XTI/REF_CLK
6 XTO
Pin Name
VD
GND
CLK_OUT
AUX_OUT
CLK_IN
XTO
XTI/REF_CLK
AD0/CS
SCL/CCLK
SDA/CDIN
# Pin Description
1 Digital Power (Input) - Positive power supply for the digital and analog sections.
2 Ground (Input) - Ground reference.
3 PLL Clock Output (Output) - PLL clock output.
4 Auxiliary Output (Output) - This pin outputs a buffered version of one of the input or output clocks,
or a status signal, depending on register configuration.
5 Frequency Reference Clock Input (Input) - Clock input for the Digital PLL frequency reference.
6 Crystal Connections (XTI/XTO) / Timing Reference Clock Input (REF_CLK) (Input/Output) -
7 XTI/XTO are I/O pins for an external crystal which may be used to generate the low-jitter PLL input
clock. REF_CLK is an input for an externally generated low-jitter reference clock.
8 Address Bit 0 (I²C) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in I²C
Mode. CS is the chip select signal in SPI Mode.
9 Control Port Clock (Input) - SCL/CCLK is the serial clock for the serial control port in I²C and SPI
mode.
10 Serial Control Data (Input/Output) - SDA is the data I/O line in I²C Mode. CDIN is the input data
line for the control port interface in SPI Mode.
DS761F3
5
5 Page 
CS2000-CP
CONTROL PORT SWITCHING CHARACTERISTICS - SPI FORMAT
Inputs: Logic 0 = GND; Logic 1 = VD; CL = 20 pF.
Parameter
Symbol
Min
Max
CCLK Clock Frequency
CCLK Edge to CS Falling
(Note 14)
CS High Time Between Transmissions
CS Falling to CCLK Edge
CCLK Low Time
CCLK High Time
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time
(Note 15)
Rise Time of CCLK and CDIN
(Note 16)
Fall Time of CCLK and CDIN
(Note 16)
Delay from Supply Voltage Stable to Control Port Ready
fccllk
tspi
tcsh
tcss
tscl
tsch
tdsu
tdh
tr2
tf2
tdpor
-
500
1.0
20
66
66
40
15
-
-
100
6
-
-
-
-
-
-
-
100
100
-
Unit
MHz
ns
µs
ns
ns
ns
ns
ns
ns
ns
µs
Notes: 14. tspi is only needed before first falling edge of CS after power is applied. tspi = 0 at all other times.
15. Data must be held for sufficient time to bridge the transition time of CCLK.
16. For fcclk < 1 MHz.
VD tdpor
CS
CCLK
CDIN
t spi tcss
t scl t sch
t r2 t f2
tcsh
t dsu tdh
Figure 6. Control Port Timing - SPI Format (Write Only)
DS761F3
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CS2000-CP.PDF ] | |
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