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PDF AK7750 Data sheet ( Hoja de datos )
| Número de pieza | AK7750 | |
| Descripción | Audio DSP | |
| Fabricantes | AKM | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AK7750 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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[ASAHI KASEI]
[AK7750]
AK7750
Audio DSP with Built-in Hands-Free Phone Features
General Description
The AK7750 is a highly integrated Audio Digital Signal Processor with a stereo audio codec in one chip.
The AK7750 combines an on-chip DSP and an ARM7 processor that can be used to create Echo
Cancellation (EC) and Noise Cancellation (NC) functions. These functions make the AK7750 a perfect
choice for hands-free phones that require suppressing acoustic echo and noise. Voice quality and noise
suppression levels can be precisely adjusted by externally setting various parameters. Additionally, no
external Flash, ROM, or RAM is required as memories for Echo and Noise Cancellation are integrated on-
chip.
By using an external microprocessor to change algorithms, the AK7750 can be used in other audio
applications including sound field enhancements like surround, volume control, parametric equalizer and
speaker compensation. These functions are simplified by the AK7750 through the integration of 64K bit
delay data RAM, a high-performance audio Codec with sample rates from 8 KHz ~ 48 KHz, and 8-
channels of Digital Audio input / output.
What’s more, the latest Surround Decoders can be also be implemented by using the certified algorithms
from various technology partners.
Features
[DSP Block]
Data Word Length: 24 bit
Machine Cycle: 27.1 ns (fastest) (768fs at 48 KHz)
Number of Steps: 768 steps max. at fs = 48 KHz
4608 steps max. at fs = 8 KHz
192 steps max. at fs = 192 KHz
Multiply: 24 x 16 -> 40 bit (enables double precision operation)
Division: 24 / 24 -> 24 bit or 16 bit
ALU: 34 bit arithmetic operation (overflow margin 4 bits)
24 bit arithmetic & logic operations
Shift: 1,2,3,4,6,8,15 Bit Left Shift with indirect shift function
1,2,3,4,8,14,15 bit Right Shift with indirect shift function
Program RAM (PRAM): 768 words x 32 bit
Coefficient RAM (CRAM): 1024 words x 16 bit
Data RAM (DRAM): 256 words x 24 bit
Offset RAM (OFRAM): 48 words x 12 bit
Delay RAM (DLRAM): 64K bits (following 3 types are selectable):
- 1K words 24 bit
- 1K words 24 bit & 2K words 16 bit (limited pointer capability)
- 4kword 16bit
Data Compression/Expansion circuits for 16 bit data handling are integrated on-chip
(Dynamic-range: 23 bit equivalent, S/N+D: 15 bit equivalent (FS)).
- In Hands-free mode, Delay RAM cannot be used.
Registers: 34 bits x 4 (ACC) [for ALU]
24 bit x 8 (TMP) [for DBUS Interface]
24 bit x 6 stage stacks (PTMP) [for DBUS Interface]
On-chip ARM7TDMI Processor:
[MS0296-E-00]
1
2005/03
1 page  
[ASAHI KASEI]
2) EESEL = “ H “
AINL+ AINL- AINR+ AINR- VREFL VCOM VREFH AOUTL
AOUTR
[AK7750]
pull down
ctrl reg sw
JX0/SDIN5A
SDIN4/JX1
SDIN3/JX2
SDIN2
SDIN1
TESTI1
TESTI2
INIT_RESET
CK_RESET
S_RESET
EESEL="H"
CKSX="H"
CKS1
CKS0
ADC
REF
SDATA_AD
SWIA
SDIN5
SDIN4
HF
SDIN3
SDIN2
SWJX0_N
SWJX1
SWJX2
SDIN1
JX0
JX1
JX2
DSP
SDOUTH
ARM
SDOUT4
SDOUT3
SDOUT2
SDOUT1
RDY
DRDY
HFST
SDINH
HFST
DAC
AVDD
AVSS
SDATA_DA
BVSS
SWQD
SWQ4 OUT4E
DVDD
DVSS
SDOUT4A
HF
OUT3E_N
SDOUT3
OUT2E_N
SDOUT2
SDOUT1
OUT1E_N
RQ
SCLK
SI
SO
RDY/EESI
DRDY/EECK
SWEE
HFST_N/EEST
CONTROLLER
EEPIF
EEST
EESI
EECK
PLL&DIVIDER
EECK_N
EESO
EEADR
XTI
XTO
CLKO
LRCLK BITCLK SMODE
LFLT
The above shows a simplified AK 7750 block diagram. It does not necessarily show the circuit diagram.
[MS0296-E-00]
5
2005/03
5 Page 
[ASAHI KASEI]
[AK7750]
Pin Pin Name
NO.
32 RDY
(EESEL=”L”)
RDY/EESI
(EESEL=”H”)
33 XTO
34 XTI
35 DVSS
36 DVDD
37 RQ
38 SO
I/O
Function
Pin Classification
O Data Write Ready pin for µC Interface (Hi-Z)
µC
This pin becomes Hi-Z when CS =”H”.
O Data Write Ready pin for uC interface/
EEP/µC
EEPROM Serial Data Input Pin
Connect this pin to SI pin of AK6512C/14C.
When data read from EEPROM is complete (EEST changes
from “L” to “H”), this pin is automatically switched to the RDY
pin function.
O Oscillator Circuit Output pin
System Clock
When a quartz crystal oscillator is used, it is connected
between XTI pin and XTO pin.
When an external clock is used, keep this pin open.
I Oscillator Circuit Output pin
When a quartz crystal oscillator is used, it is connected
between XTI pin and XTO pin.
An external clock should be fed to this pin when no quartz
crystal oscillator is used.
- Digital Ground pin 0 V
Digital Power Supply
- Digital Power Supply pin 3.3 V (typ)
I Request N pin for µC Interface
µC
µC interface is enabled when RQ =”L”. Read operations
during RUN mode should be made when RQ =”H”.
RQ should be kept “H” during the reset operation and when
an external µC is not used.
O Serial Data Output pin for µC interface
µC
This pin becomes Hi-Z state at CS =”H” when EESEL is at “L”.
39 SI
40 SCLK
41 SMODE
42 CKSX
43 DVDD
44 DVSS
45 BVSS
I Serial Data Input/Serial Data Output Control pin for µC µC
interface
If no data is input to this pin or it is not used as Serial Data
Output Control pin, set SI at “L”.
I Serial Data Clock pin for µC interface
µC
If no clock is used, set SCLK at “H”.
I Slave / Master Mode Select pin
Control
SMODE=”L”: Slave mode
SMODE=”H”: Master mode
I Master Clock Select pin
CKSX=”H”:XTI, CKSX=”L”:BITCLK_I
For normal operation, CKSX is set to “H”.
- Digital Power Supply pin 3.3 V (typ)
Digital Power Supply
- Digital Ground pin 0 V
- Ground pin (silicon substrate potential)
Analog Power Supply
Tie this pin to AVSS.
[MS0296-E-00]
11
2005/03
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AK7750.PDF ] | |
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