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PDF TC5588J-20 Data sheet ( Hoja de datos )

Número de pieza TC5588J-20
Descripción SILICON GATE CMOS STATIC RAM
Fabricantes Toshiba 
Logotipo Toshiba Logotipo



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No Preview Available ! TC5588J-20 Hoja de datos, Descripción, Manual

TOSHIBA
1l:5588P/}15/20/25/35
SILICON GATE CMOS
8,192 WORD x 8 BIT CMOS STATIC RAM
Description
The TC5588P/J is a 65,536 bit high speed CMOS static random access memory organized as 8,192 words by 8 bits and operated
from a single 5V supply. Toshiba's advanced CMOS technology and circuit design enable high speed~ration.
The TC5588P/J features low power dissipation when the device is deselected using chip enable (CE1, CE2) and has an output
enable input (OE) for fast memory access. Also, the device power between memory accesses is reduced by an automatic power
down circuit.
The TC5588P/J is suitable for use in high speed applications such as cache memory and high speed storage. All inputs and
outputs are TIL compatible. The TC5588P/J is available in a 300mil width, 28-pin DIP and SOJ suitable for high density surface
assembly.
Features
• Fast access time
- TC5588P/J-15 15ns (max.)
- TC5588P/J-20 20ns (max.)
- TC5588P/J-25 25ns (max.)
- TC5588P/J-35 35ns (max.}
• Low power dissipation
- Operation:
- TC5588P/J-15
- TC5588P/J-20
- TC5588P/J-25
- TC5588P/J-35
- Standby:
135mA (max.)
115mA (max.)
115mA (max.)
115mA (max.)
1mA (max.)
• Single 5V power supply: 5V±1 0%
• Fully static operation
• Inputs and outputs TIL compatible
• Output buffer control: OE
• Package:
- TC5588P: DIP28-P-300B
- TC5588J: SOJ28-P-300A
Pin Names
AO - A12
1/01 - 1/08
CE1, CE2
WE
OE
Voo
GND
NC
Address Inputs
Data Inputs/Outputs
Chip Enable Inputs
Write Enable Input
Output Enable Input
Power (+5V)
Ground
No Connection
Pin Connection (Top View)
TCSS88P
NC Vee
A12 WE
A7 CE2
A6 A8
AS A9
A4 All
A3 OE
A2 AtO
At m
AO 1108
VOl 1107
1/02 1/06
1103 1105
GND 1104
(DIP)
TCSS88J
NC
A12
A7
A6
AS
A4
A3
A2
At
AO
1/01
1/02.
1/03
GNO
Vee
WE
CE2
A8
A9
All
M
rAtnO
1/08
1107
1/06
VOS
1104
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
8-1

1 page




TC5588J-20 pdf
Timing Waveforms
Read Cycle (2)
ADDRESSES
CE2
m
Static RAM
tC02
toe
TC5588P/J-15/20/25/35
Dour
High Impedance
1_ _ _~tC~O~E~_ _~~IUNKNOWN
OUTPUT DATA VALID
Write Cycle 1 (5) (WE Controlled Write)
ADDRESSES
twc
tWR
UNKNOWN
CE2
m
Dour
UNKNOWN
tos
DATA STABLE
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
UNKNOWtf
8-5

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