PDF MSC7115 Data sheet ( Hoja de datos )

Número de pieza	MSC7115
Descripción	Low-Cost 16-bit DSP
Fabricantes	NXP Semiconductors
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Freescale Semiconductor Data Sheet Low-Cost 16-bit DSP with DDR Controller Document Number: MSC7115 Rev. 11, 4/2008 MSC7115 MAP-BGA–400 17 mm × 17 mm • StarCore® SC1400 DSP extended core with one SC1400 DSP core, 192 Kbyte of internal SRAM M1 memory, 16 way 16 Kbyte instruction cache (ICache), four-entry write buffer, programmable interrupt controller (PIC), and low-power Wait and Stop processing modes. • 192 Kbyte M2 memory for critical data and temporary data buffering. • 8 Kbyte boot ROM. • AHB-Lite crossbar switch that allows parallel data transfers between four master ports and six slave ports, where each port connects to an AHB-Lite bus; fixed or round robin priority programmable at each slave port; programmable bus parking at each slave port; low power mode. • Internal PLL generates up to 266 MHz clock for the SC1400 core and up to 133 MHz for the crossbar switch, DMA channels, M2 memory, and other peripherals. • Clock synthesis module provides predivision of PLL input clock; independent clocking of the internal timers and DDR module; programmable operation in the SC1400 low power Stop mode; independent shutdown of different regions of the device. • Enhanced 16-bit wide host interface (HDI16) provides a glueless connection to industry-standard microcomputers, microprocessors, and DSPs and can also operate with an 8-bit host data bus, making if fully compatible with the DSP56300 HI08 from the external host side. • DDR memory controller that supports byte enables for up to a 32-bit data bus; glueless interface to 133 MHz 14-bit page mode DDR-RAM; 14-bit external address bus supporting up to 1 Gbyte; and 16-bit or 32-bit external data bus. • Programmable memory interface with independent read buffers, programmable predictive read feature for each buffer, and a write buffer. • System control unit performs software watchdog timer function; includes programmable bus time-out monitors on AHB-Lite slave buses; includes bus error detection and programmable time-out monitors on AHB-Lite master buses; and has address out-of-range detection on each crossbar switch buses. • Event port collects and counts important signal events including DMA and interrupt requests and trigger events such as interrupts, breakpoints, DMA transfers, or wake-up events; units operate independently, in sequence, or triggered externally; can be used standalone or with the OCE10. • Multi-channel DMA controller with 32 time-multiplexed unidirectional channels, priority-based time-multiplexing between channels using 32 internal priority levels, fixed- or round-robin-priority operation, major-minor loop structure, and DONE or DRACK protocol from requesting units. • Two independent TDM modules with independent receive and transmit, programmable sharing of frame sync and clock, programmable word size (8 or 16-bit), hardware-base A-law/μ-law conversion, up to 50 Mbps data rate per TDM, up to 128 channels, with glueless interface to E1/T1 frames and MVIP, SCAS, and H.110 buses. • UART with full-duplex operation up to 5.0 Mbps. • Up to 41 general-purpose input/output (GPIO) ports. • I2C interface that allows booting from EEPROM devices up to 1 Mbyte. • Two quad timer modules, each with sixteen configurable 16-bit timers. • fieldBIST™ unit detects and provides visibility into unlikely field failures for systems with high availability to ensure structural integrity, that the device operates at the rated speed, is free from reliability defects, and reports diagnostics for partial or complete device inoperability. • Standard JTAG interface allows easy integration to system firmware and internal on-chip emulation (OCE10) module. • Optional booting external host via 8-bit or 16-bit access through the HDI16, I2C, or SPI using in the boot ROM to access serial SPI Flash/EEPROM devices; different clocking options during boot with the PLL on or off using a variety of input frequency ranges. © Freescale Semiconductor, Inc., 2004, 2008. All rights reserved. 1 page Pin Assignments Bottom View 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A NC NC NC NC NC GND HD0 HD1 HD4 HD6 HD7 HD10 HD12 HD15 CK CK DQS2 DQM1 GND GND B NC NC NC NC NC NC NC HD2 HD5 HD8 HD11 HD14 WE CKE DQS0 DQS3 DQM2 CS0 NC VDDM C NC NC NC NC NC NC NC NC HD3 HD9 HD13 CAS RAS DQS1 DQM0 DQM3 CS1 D25 D30 D24 D NC NC NC VDD VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDM VDDM VDDM VDDM VDDM VDDM GND D27 D28 VDDM E NC NC NC VDD VDD VDDIO VDDIO VDDIO VDDIO VDDIO VDDM VDD VDD VDD VDD VDDM VDDM D31 D26 GND F NC NC NC VDD VDD VDDIO GND GND GND VDDM VDDM GND GND GND VDD VDD VDD D29 D15 VDDM G NC NC NC VDD VDDIO VDDIO GND GND GND GND GND GND GND GND GND VDDM VDDM GND D13 GND H HA1 HA2 NC VDD VDDIO VDDIO GND GND GND GND GND GND GND GND GND VDDM VDDM D11 D12 D14 J HREQ HACK HA3 VDD VDDIO GND GND GND GND GND GND GND GND GND VDDM VDDM VDDM D9 VDDM D10 K HDS HDDS HA0 VDD VDDIO VDDIO GND GND GND GND GND GND GND GND GND VDDM VDD D8 GND D0 L HRW HCS1 HCS2 VDD VDDIO VDDIO VDDIO GND GND GND GND GND GND GND GND VDDM VDD D3 GND D1 M URXD UTXD SDA VDD VDD GND GND GND GND GND GND GND GND GND GND VDDM VDDM D5 VDDM D2 N VSSPLL SCL CLKIN VDD VDD VDDIO GND GND GND GND GND GND GND GND VDDM VDDM VDDM VREF D6 D4 P VDDPLL TPSEL PORESET VDD VDDIO VDDIO GND GND GND GND GND GND GND GND VDDM VDDM VDDM D16 D17 D7 R TEST0 EE0 TDO VDD VDDIO VDDIO GND VDDIO GND GND VDDM GND VDDM GND VDDM VDDM VDDM D18 D19 GND T HRESET TMS NC VDD VDD VDDIO VDDIO VDDIO VDDIO VDDM VDDM VDD VDDM VDDM VDD VDDM VDDM D22 D20 VDDM U TRST TCK NC VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDDM D23 D21 GND V TDI NC GPIA24 GPIA22 T2TD T2RD T1TD T1RFS T0TCK EVNT4 EVNT0 NC BA0 A2 A5 A10 A11 A13 NC VDDM W H8BIT GPIA26 GPIA23 GPIA19 T2TFS T2RFS T1TFS T1RD T0TFS T0RFS EVNT2 EVNT1 NC A3 A6 A7 A8 A12 VDDM GND Y GPIA25 GND GPIA21 GPIA20 T2TCK T2RCK T1TCK T1RCK TOTD T0RD T0RCK EVNT3 NMI BA1 A4 A0 A1 A9 GND VDDM Figure 3. MSC7115 Molded Array Process-Ball Grid Array (MAP-BGA), Bottom View MSC7115 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11 Freescale Semiconductor 5 5 Page Number K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 L18 (1L44X) L18 (1M88B) L19 L20 M1 M2 Pin Assignments Table 1. MSC7115 Signals by Ball Designator (continued) End of Reset Signal Names Software Controlled GPI Enabled (Default) Interrupt Enabled GPO Enabled reserved reserved reserved reserved GPIB11 reserved reserved GND GND GND GND GND GND GND GND GND VDDIO VDDIO VDDC D1 GND D3 VDDC VDDM GND GND GND GND GND GND GND GND VDDIO VDDIO VDDIO VDDC GPOB11 D2 VDDM Hardware Controlled Primary Alternate HA0 HDDS HDS/HDS or HWR/HWR HCS2/HCS2 HCS2/HCS2 HCS1/HCS1 HRW or HRD/HRD MSC7115 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11 Freescale Semiconductor 11 11 Page

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