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PDF AT28C010-12DK Data sheet ( Hoja de datos )
| Número de pieza | AT28C010-12DK | |
| Descripción | Space 1-MBit (128K x 8) Paged Parallel EEPROM | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Fast Read Access Time – 120 ns
• Automatic Page Write Operation
– Internal Address and Data Latches for 128 Bytes
– Internal Control Timer
• Fast Write Cycle Time
– Page Write Cycle Time – 10 ms Maximum
– 1 to 128-byte Page Write Operation
• Low Power Dissipation
– 50 mA Active Current
– 10 mA CMOS Standby Current
• Hardware and Software Data Protection
• DATA Polling for End of Write Detection
• High Reliability CMOS Technology
– Endurance: 5.104 Read/Modify Write Cycles @ Ground Level
– Data Retention: 10 Years
• Operating Range: 4.5V to 5.5V, -55 to +125°C
• CMOS and TTL Compatible Inputs and Outputs
• No Single Event Latch-up below a LET Threshold of 80 MeV/mg/cm2
• Tested up to a Total Dose of (according to MIL STD 883 Method 1019):
– 10 kRads (Si) Read-only Mode when Biased
– 30 kRads (Si) Read-only Mode when Unbiased
• JEDEC Approved byte-Wide Pinout
435 Mils Wide 32-Pin Flat Pack Package
AT2010-12DK Mil
Space 1-MBit
(128K x 8)
Paged Parallel
EEPROMs
AT28C010-12DK
Description
The AT28C010-12DK is a high-performance Electrically Erasable and Programmable
Read-Only Memory. Its one megabit of memory is organized as 131,072 words by 8
bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device
offers access times to 120 ns with power dissipation of just 275 mW. When the device
is deselected, the CMOS standby current is less than 10 mA.
The AT28C010-12DK is accessed like a Static RAM for the read or write cycle without
the need for external components. The device contains a 128-byte page register to
allow writing of up to 128 bytes simultaneously. During a write cycle, the address and
1 to 128 bytes of data are internally latched, freeing the address and data bus for
other operations. Following the initiation of a write cycle, the device will automatically
write the latched data using an internal control timer. The end of a write cycle can be
detected by DATA POLLING of I/O7. Once the end of a write cycle has been detected
a new access for a read or write can begin.
Atmel's 28C010 has additional features to ensure high quality in manufacturing. The
device utilizes internal error correction for extended endurance and improved data
retention characteristics. An optional software data protection mechanism is available
to guard against inadvertent writes. The device also includes an extra 128 bytes of
EEPROM for device identification or tracking.
Rev. 4259E–AERO–02/11
1 page  
Operating Modes
AT28C010-12DK
Mode
CE OE WE
Read
VIL VIL VIH
Write(1)
VIL VIH VIL
Standby
VIH X X
Write Inhibit
X X VIH
Write Inhibit
VIH X
X
Write Inhibit
X VIL X
Write Inhibit
VIL VIL VIL
Software Chip Clear
VIL VIH VIL
Software Write Protect VIL VIH VIL
High Voltage Chip Clear
VIL
VH
VIL
Output Disable
X VIH X
VIH = High Logic, “1” state, VIL = Low Logic “0” state.
X = logic “don’t care” state, High Z = high impedance state.
VH = Chip clear voltage, DOUT = Data out, and DIN = Data in.
Notes: 1. Refer to AC Programming Waveforms
I/O
DOUT
DIN
High Z
DOUT or High Z
High Z
DOUT or High Z
No operation
DIN
DIN
VIH
High Z
4259E–AERO–02/11
5
5 Page 
Chip Erase
Waveforms
AT28C010-12DK
tS = 5 msec (min.)
tW = tH = 10 msec (min.)
VH = 12.0V ± 0.5V
Software Data
Figure 1. Protection Enable Algorithm(1)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA A0
TO
ADDRESS 5555
WRITES ENABLED(2)
LOAD DATA XX
TO
ANY ADDRESS(3)
LOAD LAST BYTE
TO
LAST ADDRESS
ENTER DATA
PROTECT STATE
Notes:
1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. Write Protect state will be activated at end of write even if no other data is loaded.
3. 1 to 128 bytes of data are loaded.
4259E–AERO–02/11
11
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet AT28C010-12DK.PDF ] | |
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