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PDF FQA8N100C Data sheet ( Hoja de datos )

Número de pieza FQA8N100C
Descripción MOSFET ( Transistor )
Fabricantes Fairchild Semiconductor 
Logotipo Fairchild Semiconductor Logotipo



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No Preview Available ! FQA8N100C Hoja de datos, Descripción, Manual

FQA8N100C
N-Channel QFET® MOSFET
1000 V, 8 A, 1.45 Ω
Features
• RDS(on) = 1.45 Ω (Max.) @ VGS = 10 V, ID = 4 A
• Low Gate Charge (Typ. 53 nC)
Low Crss (Typ. 16 pF)
• 100% Avalanche Tested
March 2014
Description
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild's proprietary, planar
stripe, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the avalanche
and commutation mode. These devices are well suited for high
efficient switched mode power supplies.
D
G
D
S
TO-3PN
G
S
Absolute Maximum Ratings TC = 25°C unless otherwise noted.
Symbol
VDSS
ID
IDM
VGSS
EAS
IAR
EAR
dv/dt
PD
TJ, TSTG
TL
Parameter
Drain-Source Voltage
Drain Current
Drain Current
- Continuous (TC = 25°C)
- Continuous (TC = 100°C)
- Pulsed
Gate-Source voltage
Single Pulsed Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Power Dissipation
(TC = 25°C)
- Derate above 25°C
Operating and Storage Temperature Range
Maximum Lead Temperature for Soldering Purpose,
1/8” from Case for 5 Seconds
(Note 1)
(Note 2)
(Note 1)
(Note 1)
(Note 3)
FQA8N100C
1000
8
5
32
±30
850
8
22.5
4.0
225
1.79
-55 to +150
300
Thermal Characteristics
Symbol
RθJC
RθCS
RθJA
Parameter
Thermal Resistance, Junction-to-Case, Max.
Thermal Resistance, Case-to-Sink, Typ.
Thermal Resistance, Junction-to-Ambient, Max.
FQA8N100C
0.56
0.24
40
©2005 Fairchild Semiconductor Corporation
FQA8N100C Rev C1
1
Unit
V
A
A
A
V
mJ
A
mJ
V/ns
W
W/°C
°C
°C
Unit
°C/W
°C/W
°C/W
www.fairchildsemi.com

1 page




FQA8N100C pdf
Same Type
50KΩ as DUT
12V 200nF
300nF
VGS
10V
Qg
VGS
VDS
Qgs Qgd
IG = const.
DUT
Charge
Figure 12. Gate Charge Test Circuit & Waveform
VGS
VDS
VGS
RG
RL
VDD
DUT
VDS
90%
VGS 10%
td(on)
tr
t on
td(off)
tf
t off
Figure 13. Resistive Switching Test Circuit & Waveforms
VDS
ID
RG
L
EAS = --21-- L IAS2
BVDSS
--------------------
BVDSS - VDD
BVDSS
IAS
VDD ID (t)
VGS
DUT
VDD
VDS (t)
t p t p Time
Figure 14. Unclamped Inductive Switching Test Circuit & Waveforms
©2005 Fairchild Semiconductor Corporation
FQA8N100C Rev C1
5
www.fairchildsemi.com

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