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PDF USB2228 Data sheet ( Hoja de datos )
| Número de pieza | USB2228 | |
| Descripción | 4th Generation USB 2.0 Flash Media Controller | |
| Fabricantes | Microchip | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de USB2228 (archivo pdf) en la parte inferior de esta página. Total 25 Páginas | ||
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USB2227/USB2228
4th Generation USB 2.0 Flash Media Controller with
Integrated Card Power FETs
Highlights
• Complete System Solution for interfacing Smart-
Media™ (SM) or xD Picture Card™ (xD)1, Memory
Stick® (MS), High Speed Memory Stick (HSMS),
Memory Stick PRO (MSPRO), MS Duo™, Secure
Digital (SD), Mini-Secure Digital (Mini-SD), Trans-
Flash (SD), MultiMediaCard™ (MMC), Reduced
Size MultiMediaCard (RS-MMC), NAND Flash,
Compact Flash® (CF) and CF Ultra™ I & II, and
CF form-factor ATA hard drives to USB 2.0 bus
- Supports USB Bulk Only Mass Storage Com-
pliant Bootable BIOS
• Support for simultaneous operation of all above
devices. (only one at a time of each of the follow-
ing groups supported: CF or ATA drive, SM or XD
or NAND, SD or MMC)
• On-Chip 4-Bit High Speed Memory Stick and MS
PRO Hardware Circuitry
• On-Chip firmware reads and writes High Speed
Memory Stick and MS PRO
• 1-bit ECC correction performed in hardware for
maximum efficiency
• Hardware support for SD Security Command
Extensions
• On-chip power FETs for supplying flash media
card power with minimum board components
• USB Bus Power Certified
• 3.3 Volt I/O with 5V input tolerance on VBUS/
GPIO3
• Complete USB Specification 2.0 Compatibility for
Bus Powered Operation
- Includes USB 2.0 Transceiver
- A Bi-directional Control and a Bi-directional
Bulk Endpoint are provided.
• 8051 8 bit microprocessor
- Provides low speed control functions
- 30 Mhz execution speed at 4 cycles per
instruction average
- 12K Bytes of internal SRAM for general pur-
pose scratchpad
- 768 Bytes of internal SRAM for general pur-
pose scratchpad or program execution while
re-flashing external ROM
1.xD Picture Card not applicable to USB2227
• Double Buffered Bulk Endpoint
- Bi-directional 512 Byte Buffer for Bulk End-
point
- 64 Byte RX Control Endpoint Buffer
- 64 Byte TX Control Endpoint Buffer
• Internal or External Program Memory Interface
- 64K Byte Internal Code Space or Optional
64K Byte External Code Space using Flash,
SRAM or EPROM memory.
• On Board 24Mhz Crystal Driver Circuit
• Can be clocked by 48MHz external source
• On-Chip 1.8V Regulator for Low Power Core
Operation
• Internal PLL for 480Mhz USB 2.0 Sampling, Con-
figurable MCU clock
• Supports firmware upgrade via USB bus if “boot
block” Flash program memory is used
• 15 GPIOs for special function use: LED indica-
tors, button inputs, power control to memory
devices, etc.
- Inputs capable of generating interrupts with
either edge sensitivity
- Attribute bit controlled features:
- Activity LED polarity/operation/blink rate
- Full or Partial Card compliance checking
- Bus or Self Powered
- LUN configuration and assignment
- Write Protect Polarity
- SmartDetach Detach from USB when no
Card Inserted for Notebook apps
- Cover Switch operation for xD compliance
- Inquiry Command operation
- SD Write Protect operation
- Older CF card support
- Force USB 1.1 reporting
- Internal or External Power FET operation
• Compatible with Microsoft WinXP, WinME, Win2K
SP3, Apple OS10, Softconnex, and Linux Multi-
LUN Mass Storage Class Drivers
• Win2K, Win98/98SE and Apple OS8.6 and OS9
Multi-LUN Mass Storage Class Drivers available
from Microchip
• 128-Pin VTQFP RoHS Compliant Package
(14mm x 14mm footprint, 1.0mm height)
2007-2016 Microchip Technology Inc.
DS00002256A-page 1
1 page  
USB2227/USB2228
2.0 PIN CONFIGURATION
FIGURE 2-1:
USB2227/USB2228 128-PIN VTQFP
VSS
RBIAS
ATEST
VDD33
VDD18PLL
XTAL1
XTAL2
VSSPLL
GPIO9
VDD18
GPIO7
VDD33
GPIO6/ROMEN
GPIO5
GPIO4
VSS
GPIO2
GPIO1
nRESET
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
MA12
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
USB2227/2228
VTQFP 128
(Top View)
64 CF_SA2
63 CF_SA1
62 CF_SA0
61 CF_nCS1
60 CF_nCS0
59 CF_nRESET
58 CF_nIOW
57 CF_nIOR
56 CF_IORDY
55 CF_IRQ
54 CF_nCD2
53 CF_nCD1
52 CF_D15
51 CF_D14
50 CF_D13
49 VDD18
48 CF_D12
47 VSS
46 CF_D11
45 CF_D10
44 GPIO11
43 VDD33
42 GPIO8
41 CF_D9
40 CF_D8
39 CF_D7
38 CF_D6
37 CF_D5
36 CF_D4
35 CF_D3
34 CF_D2
33 CF_D1
2007-2016 Microchip Technology Inc.
DS00002256A-page 5
5 Page 
USB2227/USB2228
Symbol
XTAL1/
CLKIN
XTAL2
MD[7:0]
MA[15:3]
MA2/
SEL_CLKDRV
128-Pin
VTQFP
102
103
12
11
10
9
8
7
6
5
4
2
1
128
127
126
125
124
123
122
121
120
119
118
Buffer Type
Description
ICLKx Crystal Input/External Clock Input:
OCLKx
24Mhz Crystal or external clock input.
This pin can be connected to one terminal of the crystal or can
be connected to an external 24Mhz clock when a crystal is not
used.
Note:
The MA[2:0] pins will be sampled while nRESET is
asserted, and the value will be latched upon nRESET
negation. This will determine the clock source and
value.
Crystal Output:
24Mhz Crystal
This is the other terminal of the crystal, or left open when an
external clock source is used to drive XTAL1/CLKIN. It may not
be used to drive any external circuitry other than the crystal
circuit.
Memory I/O Interface
I/O8PU Memory Data Bus:
When ROMEN bit of GPIO_IN1 register = 0, these signals are
used to transfer data between the internal CPU and the external
program memory.
These pins have internally controlled weak pull-up resistors.
O8 Memory Address Bus:
These signals address memory locations within the external
memory.
I/O8PD Memory Address Bus:
MA2 Addresses memory locations within the external memory.
SEL_CLKDRV. During nRESET assertion, this pins will select the
operating clock mode (crystal or externally driven clock source),
and a weak pull-down resistor is enabled. When nRESET is
negated, the value will be internally latched and this pin will revert
to MA2 functionality, the internal pull-down will be disabled.
‘0’ = Crystal operation (24MHz only)
‘1’ = Externally driven clock source (24MHz or 48MHz)
Note: If the latched value is ‘1’, then the MA2 pin is tri-stated
when the following conditions are true:
1. IDLE bit (PCON.0) is 1.
2. INT2 is negated
3. SLEEP bit of CLOCK_SEL is 1.
If the latched value is ‘0’, then the MA2 pin will function identically
to the MA[15:3] pins at all times (other than during nRESET
assertion).
2007-2016 Microchip Technology Inc.
DS00002256A-page 11
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet USB2228.PDF ] | |
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