PDF MC9328MX1 Data sheet ( Hoja de datos )

Número de pieza	MC9328MX1
Descripción	i.MX Integrated Portable System Processor
Fabricantes	Freescale Semiconductor
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No Preview Available ! Freescale Semiconductor Data Sheet: Technical Data MC9328MX1 Document Number: MC9328MX1 Rev. 7, 12/2006 MC9328MX1 Package Information Plastic Package Case 1304B-01 (MAPBGA–225) Ordering Information See Table 1 on page 3 1 Introduction The i.MX Family of applications processors provides a leap in performance with an ARM9™ microprocessor core and highly integrated system functions. The i.MX family specifically addresses the requirements of the personal, portable product market by providing intelligent integrated peripherals, an advanced processor core, and power management capabilities. The MC9328MX1 (i.MX1) processor features the advanced and power-efficient ARM920T™ core that operates at speeds up to 200 MHz. Integrated modules, which include a USB device, an LCD controller, and an MMC/SD host controller, support a suite of peripherals to enhance portable products seeking to provide a rich multimedia experience. It is packaged in a 256-contact Mold Array Process-Ball Grid Array (MAPBGA). Figure 1 shows the functional block diagram of the i.MX1 processor. Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 Signals and Connections . . . . . . . . . . . . . . . 4 3 Electrical Characteristics . . . . . . . . . . . . . . 22 4 Functional Description and Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5 Pin-Out and Package Information . . . . . . . . 96 6 Product Documentation . . . . . . . . . . . . . . . . 98 Contact Information . . . . . . . . . . . . . . . Last Page Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. © Freescale Semiconductor, Inc., 2004, 2005, 2006. All rights reserved. 1 page Signal Name SDIBA [3:0] MA [11:10] MA [9:0] DQM [3:0] CSD0 CSD1 RAS CAS SDWE SDCKE0 SDCKE1 SDCLK RESET_SF EXTAL16M XTAL16M EXTAL32K XTAL32K CLKO RESET_IN RESET_OUT POR TRST TDO TDI TCK TMS Signals and Connections Table 2. i.MX1 Signal Descriptions (Continued) Function/Notes SDRAM interleave addressing mode bank address multiplexed with address signals A [19:16]. These signals are logically equivalent to core address p_addr [12:9] in SDRAM cycles. SDRAM address signals SDRAM address signals which are multiplexed with address signals A [10:1]. MA [9:0] are selected on SDRAM cycles. SDRAM data enable SDRAM Chip-select signal which is multiplexed with the CS2 signal. These two signals are selectable by programming the system control register. SDRAM Chip-select signal which is multiplexed with CS3 signal. These two signals are selectable by programming the system control register. By default, CSD1 is selected, so it can be used as boot chip-select by properly configuring BOOT [3:0] input pins. SDRAM Row Address Select signal SDRAM Column Address Select signal SDRAM Write Enable signal SDRAM Clock Enable 0 SDRAM Clock Enable 1 SDRAM Clock Not Used Clocks and Resets Crystal input (4 MHz to 16 MHz), or a 16 MHz oscillator input when the internal oscillator circuit is shut down. Crystal output 32 kHz crystal input 32 kHz crystal output Clock Out signal selected from internal clock signals. Master Reset—External active low Schmitt trigger input signal. When this signal goes active, all modules (except the reset module and the clock control module) are reset. Reset Out—Internal active low output signal from the Watchdog Timer module and is asserted from the following sources: Power-on reset, External reset (RESET_IN), and Watchdog time-out. Power On Reset—Internal active high Schmitt trigger input signal. The POR signal is normally generated by an external RC circuit designed to detect a power-up event. JTAG Test Reset Pin—External active low signal used to asynchronously initialize the JTAG controller. Serial Output for test instructions and data. Changes on the falling edge of TCK. Serial Input for test instructions and data. Sampled on the rising edge of TCK. Test Clock to synchronize test logic and control register access through the JTAG port. Test Mode Select to sequence the JTAG test controller’s state machine. Sampled on the rising edge of TCK. Freescale Semiconductor MC9328MX1 Technical Data, Rev. 7 5 5 Page I/O Supply BGA Voltage Pin NVDD1 NVDD1 K8 B1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 C2 C1 D2 D1 D3 E2 E3 E1 F2 F4 E4 A1 H5 F1 F3 G2 G3 F5 G4 G1 H2 H3 Table 3. MC9328MX1 Signal Multiplexing Scheme Primary Alternate GPIO Signal NVDD1 A24 D31 A23 D30 A22 D29 A21 D28 A20 D27 A19 D26 VSS NVDD1 A18 D25 A17 D24 A16 D23 A15 D22 A14 Dir Pull-up Signal Dir Mux Pull-up Ain Static O ETMTRACESYN O PA0 69K SPI2_CLK C I/O 69K O ETMTRACECLK O PA31 69K I/O 69K O ETMPIPESTAT2 O PA30 I/O 69K 69K O ETMPIPESTAT1 O PA29 I/O 69K O ETMPIPESTAT0 O PA28 69K 69K I/O 69K O ETMTRACEPKT3 O PA27 I/O 69K 69K Static Static O ETMTRACEPKT2 O PA26 I/O 69K O ETMTRACEPKT1 O PA25 69K 69K I/O 69K O ETMTRACEPKT0 O PA24 I/O 69K O I/O 69K 69K O Bin Aout RESE State (At/After) Default L Pull-H L Pull-H L Pull-H L Pull-H L Pull-H L Pull-H A24 A23 A22 A21 A20 A19 L Pull-H L Pull-H L Pull-H L Pull-H L A18 A17 A16 11 Page

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