PDF AD9162 Data sheet ( Hoja de datos )

Número de pieza	AD9162
Descripción	RF Digital-to-Analog Converters
Fabricantes	Analog Devices
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No Preview Available ! Data Sheet 11-Bit/16-Bit, 12 GSPS, RF Digital-to-Analog Converters AD9161/AD9162 FEATURES DAC update rate up to 12 GSPS (minimum) Direct RF synthesis at 6 GSPS (minimum) DC to 2.5 GHz in baseband 1× bypass mode DC to 6 GHz in 2× nonreturn-to-zero (NRZ) mode 1.5 GHz to 7.5 GHz in Mix-Mode Bypassable interpolation (1× or bypass mode) 2×, 3×, 4×, 6×, 8×, 12×, 16×, 24× Excellent dynamic performance APPLICATIONS Broadband communications systems DOCSIS 3.1 cable modem termination system (CMTS)/ video on demand (VOD)/edge quadrature amplitude modulation (EQAM) Wireless communications infrastructure W-CDMA, LTE, LTE-A, point to point Instrumentation, automatic test equipment (ATE) Radars and jammers GENERAL DESCRIPTION In baseband mode, wide bandwidth capability combines with high dynamic range to support DOCSIS 3.1 cable infrastructure compliance from the minimum of two carriers to full maximum spectrum of 1.794 GHz. A 2× interpolator filter (FIR85) enables the AD9161/AD9162 to be configured for lower data rates and converter clocking to reduce the overall system power and ease the filtering requirements. In Mix-Mode™ operation, the AD9161/ AD9162 can reconstruct RF carriers in the second and third Nyquist zones up to 7.5 GHz while still maintaining exceptional dynamic range. The output current can be programmed from 8 mA to 38.76 mA. The AD9161/AD9162 data interface consists of up to eight JESD204B serializer/deserializer (SERDES) lanes that are programmable in terms of lane speed and number of lanes to enable application flexibility. A serial peripheral interface (SPI) can configure the AD9161/ AD9162 and monitor the status of all registers. The AD9161/ AD9162 are offered in an 165-ball, 8.0 mm × 8.0 mm, 0.5 mm pitch, CSP_BGA package and in an 169-ball, 11 mm × 11 mm, 0.8 mm pitch, CSP_BGA package, including a leaded ball option for the AD9162. The AD9161/AD91621 are high performance, 11-bit/16-bit PRODUCT HIGHLIGHTS digital-to-analog converters (DACs) that supports data rates to 6 GSPS. The DAC core is based on a quad-switch architecture coupled with a 2× interpolator filter that enables an effective DAC update rate of up to 12 GSPS in some modes. The high dynamic range and bandwidth makes these DACs ideally suited for the most demanding high speed radio frequency (RF) DAC applications. 1. High dynamic range and signal reconstruction bandwidth supports RF signal synthesis of up to 7.5 GHz. 2. Up to eight lanes JESD204B SERDES interface flexible in terms of number of lanes and lane speed. 3. Bandwidth and dynamic range to meet DOCSIS 3.1 compliance with margin. FUNCTIONAL BLOCK DIAGRAM RESET IRQ ISET VREF SDIO SDO CS SCLK SERDIN0± SERDIN7± SYNCOUT± SYSREF± SPI JESD HB 2× HB 3× AD9161/AD9162 HB 2× NCO VREF NRZ RZ MIX INV SINC DAC CORE OUTPUT± HB TO JESD CLOCK 2×, TO DATAPATH DISTRIBUTION 4×, 8× TX_ENABLE Figure 1. CLK± 1 Protected by U.S. Patents 6,842,132 and 7,796,971. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com 1 page Data Sheet Parameter SERDES Supply Currents VDD_1P2 = 1.2 V DVDD_1P2 = 1.2 V PLL_LDO_VDD12 = 1.2 V SYNC_VDD_3P3 = 3.3 V 8 LANES, 6× INTERPOLATION (80%), 3 GSPS Analog Supply Currents VDD25_DAC = 2.5 V VDD12A = 1.2 V VDD12_CLK = 1.2 V VNEG_N1P2 = −1.2 V Digital Supply Currents DVDD = 1.2 V IOVDD1 = 2.5 V SERDES Supply Currents VDD_1P2 = 1.2 V DVDD_1P2 = 1.2 V PLL_LDO_VDD12 = 1.2 V SYNC_VDD_3P3 = 3.3 V NCO ONLY MODE, 5 GSPS Analog Supply Currents VDD25_DAC = 2.5 V VDD12A = 1.2 V VDD12_CLK = 1.2 V VNEG_N1P2 = −1.2 V Digital Supply Currents DVDD = 1.2 V IOVDD1 = 2.5 V SERDES Supply Currents VDD_1P2 = 1.2 V DVDD_1P2 = 1.2 V PLL_LDO_VDD12 = 1.2 V SYNC_VDD_3P3 = 3.3 V 8 LANES, 4× INTERPOLATION (80%), 5 GSPS Analog Supply Currents VDD25_DAC = 2.5 V VDD12A = 1.2 V VDD12_CLK = 1.2 V VNEG_N1P2 = −1.2 V Digital Supply Currents DVDD = 1.2 V (Includes VDD12_DCD/DLL) DVDD = 1.2 V IOVDD1 = 2.5 V SERDES Supply Currents VDD_1P2 = 1.2 V DVDD_1P2 = 1.2 V PLL_LDO_VDD12 = 1.2 V SYNC_VDD_3P3 = 3.3 V Test Conditions/Comments Includes VTT_1P2, BIAS_VDD_1P2 Connected to PLL_CLK_VDD12 NCO on, FIR85 on Includes VDD12_DCD/DLL Includes VTT_1P2, BIAS_VDD_1P2 Connected to PLL_CLK_VDD12 AD9161/AD9162 Min Typ Max Unit 425.5 62 84.4 9.3 550 86 106 11 mA mA mA mA 93.8 3.7 228.7 −120.7 598.4 2.5 443.4 72.3 81.8 9.4 mA µA mA mA mA mA mA mA mA mA −119 93.7 10 340.6 −112 100 150 432 mA µA mA mA Includes VDD12_DCD/DLL 425.5 2.5 753 2.7 mA mA Includes VTT_1P2, BIAS_VDD_1P2 Connected to PLL_CLK_VDD12 NCO on, FIR85 off (unless otherwise noted) 1.4 34 mA 1.0 14.1 mA 0.13 1.5 mA 0.32 0.43 mA At 6 GSPS −127.4 102 80 340.5 408 −120.2 108 150 432.4 mA µA mA mA mA NCO on, FIR85 off NCO off, FIR85 on NCO on, FIR85 on NCO on, FIR85 on, at 6 GSPS 665.4 706.5 894.6 1090 2.5 1033 2.7 mA mA mA mA mA Includes VTT_1P2, BIAS_VDD_1P2 Connected to PLL_CLK_VDD12 411.2 52.1 85.8 9.3 550 73 105 11 mA mA mA mA Rev. A \| Page 5 of 139 5 Page Data Sheet AD9161/AD9162 Table 10. AD9162 Specifications Parameter SPURIOUS-FREE DYNAMIC RANGE (SFDR)1 Single Tone, fDAC = 5000 MSPS fOUT = 70 MHz fOUT = 500 MHz fOUT = 1000 MHz fOUT = 2000 MHz fOUT = 4000 MHz Single Tone, fDAC = 5000 MSPS fOUT = 70 MHz fOUT = 500 MHz fOUT = 1000 MHz fOUT = 2000 MHz fOUT = 4000 MHz DOCSIS fOUT = 70 MHz fOUT = 70 MHz fOUT = 70 MHz fOUT = 950 MHz fOUT = 950 MHz fOUT = 950 MHz Wireless Infrastructure fOUT = 960 MHz fOUT = 1990 MHz ADJACENT CHANNEL POWER fOUT = 877 MHz fOUT = 877 MHz fOUT = 1887 MHz fOUT = 1980 MHz INTERMODULATION DISTORTION fOUT = 900 MHz fOUT = 900 MHz fOUT = 1800 MHz fOUT = 1800 MHz NOISE SPECTRAL DENSITY (NSD) Single Tone, fDAC = 5000 MSPS fOUT = 550 MHz fOUT = 960 MHz fOUT = 1990 MHz SINGLE SIDEBAND (SSB) PHASE NOISE AT OFFSET 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz Test Conditions/Comments With Marki Microwave BAL-0006SMG2 FIR85 enabled −6 dBFS, shuffle enabled FIR85 enabled fDAC = 3076 MSPS Single carrier Four carriers Eight carriers Single carriers Four carriers Eight carriers fDAC = 5000 MSPS Two-carrier GSM signal at −9 dBFS; across 925 MHz to 960 MHz band Two-carrier GSM signal at −9 dBFS; across 1930 MHz to 1990 MHz band fDAC = 5000 MSPS One carrier, first adjacent channel Two carriers, first adjacent channel One carriers, first adjacent channel Four carriers, first adjacent channel fDAC = 5000 MSPS, two-tone test 0 dBFS −6 dBFS, shuffle enabled 0 dBFS −6 dBFS, shuffle enabled Min Typ −82 −75 −65 −70 −60 −75 −75 −70 −75 −65 −70 −70 −67 −70 −68 −64 −85 −81 −79 −76 −74 −70 −80 −80 −68 −78 Max fOUT = 3800 MHz, fDAC = 4000 MSPS −168 −167 −164 −119 −125 −135 −144 −156 1 See the Clock Input section for more details on optimizing SFDR and reducing the image of the fundamental with clock input tuning. 2 The Marki Microwave BAL-0006SMG is used on the AD9162-FMC-EBZ evaluation board. Unit dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBm/Hz dBm/Hz dBm/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz Rev. A \| Page 11 of 139 11 Page

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