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PDF uP1707S Data sheet ( Hoja de datos )
| Número de pieza | uP1707S | |
| Descripción | High-Efficiency Synchronous-Rectified Buck Converter | |
| Fabricantes | uPI Semiconductor | |
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Hay una vista previa y un enlace de descarga de uP1707S (archivo pdf) en la parte inferior de esta página. Total 13 Páginas | ||
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uP1707S
3A, 23V, 340K High-Efficiency
Synchronous-Rectified Buck Converter
General Description
Features
The uP1707S is a high-efficiency synchronous-rectified 4.5V to 23V Input Voltage Range
buck converter with internal power switch. With internal Adjustable Output from 0.925V to 20V
low RDS(ON) switches, the high-efficiency buck converter
is capable of delivering 3A output current over a wide input
3A Output Current
voltage range from 4.5V to 23V. The output voltage is Accurate Reference: 0.925V ( +1.5%)
adjustable from 0.925V to 20V by a voltage divider. Other Up to 95% Conversion Efficiency
features for the buck converter include adjust soft-start,
chip enable, over-voltage, under-voltage, over- Integrated Low RDS(ON) Upper and Lower MOSFET
temperature and over-current protections. It is available
Switches: 100mΩ
in a space saving PSOP-8L package.
Current Mode PWM Operation
Ordering Information
Constant 340kHz Fixed-Frequency Operation
Programmable Soft-Start
Order Number
Package Type Top Marking Integrated Boot Diode
uP1707SSW8
PSOP-8L
uP1707S
Over Voltage and Under Voltage Protection
Note:
Over Temperature and Over Current Protection
(1) Please check the sample/production availability with Frequency Decay Mode During UVP
uPI representatives.
(2) uPI products are compatible with the current IPC/
PSOP-8L Package
JEDEC J-STD-020 requirement. They are halogen-free, RoHS Compliant and Halogen Free
RoHS compliant and 100% matte tin (Sn) plating that are
suitable for use in SnPb or Pb-free soldering processes.
Applications
Pin Configuration Battery-Powered Portable Devices
MP3 Players
BOOT
VIN
LX
GND
18
27
GND
36
45
PSOP - 8
SS
EN
COMP
FB
Digital Still Cameras
Wireless and DSL Modems
Personal Information Appliances
802.11 WLAN Power Supplies
FPGA/ASIC Power Supplies
Laptop, Palmtops, Notebook Computers
Portable Information Appliances
uP1707S-DS-P0000, Oct. 2013
www.upi-semi.com
1
1 page  
regulation and drop according to load. Eventually under
voltage protection will be triggered when VFB < 0.3V
(typical).
When the output is shorted to ground, the current limit
function activates immediately, and VOUT will be pulled
down very fast. Eventually the under voltage protection
will be triggered, and the IC will shut down to protect
external components. The IC will restart after the UVP
retry delay, and the above behavior may repeat if the output
short condition is not released. This is the so-called Short
Circuit Protection (SCP).
Under Voltage Protection
The uP1707S continuously monitors FB voltage for under
voltage protection. When V < 0.3V (typical), the uP1707S
FB
triggers under voltage protection and enters frequency
decay mode which the switching frequency of the
uP1707S will decrease linearly according to the FB voltage
drop. Eventually when VFB = 0V, the switching frequency
of the uP1707S will be clamped at 110kHz. After triggering
UVP, the SS voltage is also discharged to 0V. After VSS =
0V, the uP1707S will try to re-soft-start to establish the
output voltage once again. In the end of re-soft-start (V
SS
= 1.2V), if the UVP condition is still not relieved, the
uP1707S will turn-off all high-side and low-side MOSFETs
and re-try to soft start every 8ms.
Over Voltage Protection
The uP1707S continuously monitors FB voltage for over
voltage protection. When V > 1.1V (typical), the uP1707S
FB
triggers over voltage protection and the low-side MOSFET
is turned on while high-side MOSFET is turned off to
discharge the output voltage. At any time if the OVP
condition is relieved, the uP1707S will restart the soft start
sequence.
Over Temperature Protection
The OTP is triggered and shuts down the uP1707S if the
junction temperature is higher than 160OC. The OTP is a
non-latch type protection. The uP1707S automatically
initiates another soft start cycle if the junction temperature
drops below 130OC.
uP1707S
Functional Description
uP1707S-DS-P0000, Oct. 2013
www.upi-semi.com
5
5 Page 
uP1707S
Application Information
However, care must be taken when these capacitors are
used at the input and the output. When a ceramic capacitor
is used at the input and the power is supplied by a wall
adapter through long wires, a load step at the output can
induce ringing at the input, VIN. At best, this ringing can
couple to the output and be mistaken as loop instability. At
worst, a sudden inrush of current through the long wires
can potentially cause a voltage spike at VIN, large enough
to damage the part. When choosing the input and output
ceramic capacitors, choose the X5R or X7R dielectric
formulations. These dielectrics have the best temperature
and voltage characteristics of all the ceramics for a given
value and size.
Checking Transient Response
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, VOUT immediately shifts by an amount
equal to (ΔIOUT x ESR), where ESR is the effective series
resistance of COUT. ΔIOUT also begins to discharge or
charge COUT, which generates a feedback error signal.
The regulator loop then acts to return VOUT to its steady
state value. During this recovery time VOUT can be
monitored for overshoot or ringing that would indicate a
stability problem.
PCB Layout Considerations
High switching frequencies and relatively large peak
currents make the PCB layout a very important part of
switching mode power supply design. Good design
minimizes excessive EMI on the feedback paths and
voltage gradients in the ground plane, both of which can
result in instability or regulation errors. Follow the PCB
layout guidelines for optimal performance of uP1707S.
1 For the main current paths, keep their traces short,
direct and wide.
2 Put the input/output capacitors as close as possible to
the device pins.
3 LX node is with high frequency voltage swing and
should be kept small area. Keep analog components
away from LX node to prevent stray capacitive noise
pick-up.
4 Connect feedback network behind the output
capacitors. Place the feedback components near the
uP1784 and keep the loop area small. .
5 A ground plane is preferred, but if not available, keep
the signal and power grounds separated with small
signal components returning to the GND pin at one
point. They should not share the high current path of
CIN or COUT.
6 Flood all unused areas on all layers with copper.
Flooding with copper will reduce the temperature rise
of power components. These copper areas should be
connected to VIN or GND.
7 An example of 2-layer PCB layout is shown in Figure
1 for reference.
Via to CBOOT
VIN Plane
18
27
GND
36
45
VOUT Plane
Via to BOOT
Via to GND
Figure 1. Top Layer Layout Example.
uP1707S-DS-P0000, Oct. 2013
www.upi-semi.com
11
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet uP1707S.PDF ] | |
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