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What is HI-3583A?

This electronic component, produced by the manufacturer "HOLTIC", performs the same function as "3.3V Terminal IC".


HI-3583A Datasheet PDF - HOLTIC

Part Number HI-3583A
Description 3.3V Terminal IC
Manufacturers HOLTIC 
Logo HOLTIC Logo 


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July 2013
HI-3582A, HI-3583A
ARINC 429
3.3V Terminal IC with High-Speed Interface
GENERAL DESCRIPTION
The HI-3582A/HI-3583A from Holt Integrated Circuits are
silicon gate CMOS devices for interfacing a 16-bit parallel
data bus directly to the ARINC 429 serial bus. The
HI-3582A/HI-3583A design offers a high-speed host CPU
interface compared with the earlier HI-3582/HI-3583
products. The device provides two receivers each with
label recognition, 32 by 32 FIFO, and analog line receiver.
Up to 16 labels may be programmed for each receiver.
The independent transmitter has a 32 X 32 FIFO and a
built-in line driver. The status of all three FIFOs can be
monitored using the external status pins, or by polling the
HI-3582A/HI-3583A status register. Other features include
a programmable option of data or parity in the 32nd bit,
and the ability to unscramble the 32 bit word. Also,
versions are available with different values of input
resistance and output resistance to allow users to more
easily add external lightning protection circuitry.
The 16-bit parallel data bus exchanges the 32-bit ARINC
data word in two steps when either loading the transmitter
or interrogating the receivers. The databus and all control
signals are 3.3V CMOS compatible.
The HI-3582A/HI-3583A apply the ARINC protocol to the
receivers and transmitter. Timing is based on a 1 Mega-
hertz clock.
APPLICATIONS
• Avionics data communication
• Serial to parallel conversion
• Parallel to serial conversion
PIN CONFIGURATIONS (Top View)
(See page 14 for additional pin configuration)
See Note below
N/C - 1
D/R1 - 2
FF1 - 3
HF1 - 4
D/R2 - 5
FF2 - 6
HF2 - 7
SEL - 8
EN1 - 9
EN2 - 10
N/C - 11
BD15 - 12
BD14 - 13
BD13 - 14
BD12 - 15
BD11 - 16
HI-3582APCI
HI-3582APCT
HI-3582APCM
&
HI-3583APCI
HI-3583APCT
HI-3583APCM
48 - CWSTR
47 - ENTX
46 - N/C
45 - V+
44 - TXBOUT
43 - TXAOUT
42 - V-
41 - N/C
40 - FFT
39 - HFT
38 - TX/R
37 - PL2
36 - PL1
35 - BD00
34 - BD01
33 - N/C
(Note: All 3 VDD pins must be connected to the same 3.3V supply)
64 - Pin Plastic 9mm x 9mm
Chip-Scale Package
FEATURES
· ARINC specification 429 compatible
· High-speed 3.3V logic interface
· Dual receiver and transmitter interface
· Analog line driver and receivers connect directly to
ARINC bus
· Programmable label recognition
· On-chip 16 label memory for each receiver
· 32 x 32 FIFOs each receiver and transmitter
· Independent data rate selection for transmitter and
each receiver
· Status register
· Data scramble control
· 32nd transmit bit can be data or parity
· Self test mode
· Low power
· Industrial & extended temperature ranges
FF1 - 1
HF1 - 2
D/R2 - 3
FF2 - 4
HF2 - 5
SEL - 6
EN1 - 7
EN2 - 8
BD15 - 9
BD14 - 10
BD13 - 11
BD12 - 12
BD11 - 13
HI-3582APQI
HI-3582APQT
HI-3582APQM
&
HI-3583APQI
HI-3583APQT
HI-3583APQM
39 - N/C
38 - CWSTR
37 - ENTX
36 - V+
35 - TXBOUT
34 - TXAOUT
33 - V-
32 - FFT
31 - HFT
30 - TX/R
29 - PL2
28 - PL1
27 - BD00
(DS3582A Rev. C)
52 - Pin Plastic Quad Flat Pack (PQFP)
HOLT INTEGRATED CIRCUITS
www.holtic.com
07/13

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HI-3583A equivalent
HI-3582A, HI-3583A
FUNCTIONAL DESCRIPTION (cont.)
RECEIVER PARITY
The 32nd bit of received ARINC words stored in the receive FIFO
is used as a Parity Flag indicating whether good Odd parity is
received from the incoming ARINC word.
ARINC words which do not meet the necessary 9th and 10th
ARINC bit or label matching are ignored and are not loaded into
the receive FIFO. The following table describes this operation.
Odd Parity Received
The parity bit is reset to indicate correct parity was received
and the resulting word is then written to the receive FIFO.
Even Parity Received
The receiver sets the 32nd bit to a “1”, indicating a parity error
and the resulting word is then written to the receive FIFO.
Therefore, the 32nd bit retrieved from the receiver FIFO will
always be “0” when valid (odd parity) ARINC 429 words are
received.
RETRIEVING DATA
Once 32 valid bits are recognized, the receiver logic generates an
End of Sequence (EOS). Depending upon the state of control
register bits CR2-CR11, the received ARINC 32-bit word is then
checked for correct decoding and label matching before being
loaded into the 32 x 32 receive FIFO.
CR2(3) ARINC word CR6(9) ARINC word
matches
bits 9,10
label
match
CR7,8 (10,11)
0 X0 X
1 No 0
X
1 Yes 0
X
0 X 1 No
0 X 1 Yes
1 Yes 1
No
1 No 1 Yes
1 No 1 No
1 Yes 1 Yes
FIFO
Load FIFO
Ignore data
Load FIFO
Ignore data
Load FIFO
Ignore data
Ignore data
Ignore data
Load FIFO
SEL
EN
MUX
CONTROL
TO PINS
32 TO 16 DRIVER
R/W
CONTROL
CONTROL
BITS
HF
FF
D/R
FIFO
LOAD
CONTROL
CONTROL
BIT
32 X 32
FIFO
/ LABEL /
DECODE
COMPARE
CONTROLBITS
CR0, CR14
CLOCK
OPTION
16 x 8
LABEL
MEMORY
EOS
32 BIT SHIFT REGISTER
DATA PARITY
CHECK
BIT CLOCK
32ND
BIT
BIT
COUNTER
AND
END OF
SEQUENCE
ONES
NULL
SHIFT REGISTER
SHIFT REGISTER
WORD GAP
WORD GAP
TIMER
BIT CLOCK
START
SEQUENCE
CONTROL
END
CLOCK
ZEROS
SHIFT REGISTER
ERROR
DETECTION
ERROR
CLOCK
FIGURE 2. RECEIVER BLOCK DIAGRAM
HOLT INTEGRATED CIRCUITS
5
CLK


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Featured Datasheets

Part NumberDescriptionMFRS
HI-3583The function is 3.3V Terminal IC. HOLTICHOLTIC
HI-3583AThe function is 3.3V Terminal IC. HOLTICHOLTIC

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