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PDF 8L30210 Data sheet ( Hoja de datos )
| Número de pieza | 8L30210 | |
| Descripción | Crystal or Differential to LVCMOS/LVTTL Clock Buffer | |
| Fabricantes | IDT | |
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Crystal or Differential to LVCMOS/
LVTTL Clock Buffer
8L30210
DATA SHEET
General Description
The 8L30210 is a low skew, 1-to-10 LVCMOS / LVTTL Fanout Buffer.
The low impedance LVCMOS/LVTTL outputs are designed to drive
50 series or parallel terminated transmission lines.
The 8L30210 is characterized at full 3.3V and 2.5V, mixed 3.3V/2.5V,
3.3V/1.8V, 3.3V/1.5V, 2.5V/1.8V and 2.5V/1.5V output operating
supply modes. The input clock is selected from two differential clock
inputs or a crystal input. The differential input can be wired to accept
a single-ended input. The internal oscillator circuit is automatically
disabled if the crystal input is not selected.
Features
• Ten LVCMOS / LVTTL outputs up to 200MHz
• Differential input pair can accept the following differential input
levels: LVPECL, LVDS, HCSL
• Crystal Oscillator Interface
• Crystal input frequency range: 10MHz to 40MHz
• Additive RMS phase jitter: 30fs (typical)
• Synchronous output enable to avoid clock glitch
• Power supply modes:
Core / Output
3.3V / 3.3V
2.5V / 2.5V
3.3V / 2.5V
3.3V / 1.8V
3.3V / 1.5V
2.5V / 1.8V
2.5V / 1.5V
• Supports case temperature up to 105°C
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
Block Diagram
Pin Assignment
32 31 30 29 28 27 26 25
Q0 1
24 Q9
VDDO 2
23 VDDO
00
Q1 3
22 Q8
GNDO 4
21 GNDO
01 8L30210
Q2 5
20 Q7
VDDO 6
19 VDDO
1x
Q3 7
18 Q6
Q4 8
17 Q5
9 10 11 12 13 14 15 16
8L30210 REVISION 2 11/24/15
32-pin, 5mm x 5mm VFQFN Package
1 ©2015 Integrated Device Technology, Inc.
1 page  
8L30210 DATA SHEET
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, VDD
Inputs, VI
CLKX, nCLKX
XTAL_IN
Other Inputs
Outputs, VO
Junction Temperature, TJ
Storage Temperature, TSTG
Rating
3.6V
3.6V
0V to 2V
-0.5V to VDD + 0.5V
-0.5V to VDDO + 0.5V
125°C
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = 3.3V±5%, VDDO = 3.3V±5% or 2.5V±5% or 1.8V±0.15V or 1.5V±0.1V,
TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VDD Power Supply Voltage
3.135 3.3 3.465 V
3.135 3.3 3.465 V
VDDO
Output Supply Voltage
2.375 2.5 2.625 V
1.65 1.8 1.95 V
1.4 1.5 1.6 V
IDD
IDDO
Power Supply Current
Output Supply Current
No Clock Input, Outputs Unloaded
OE = 1, VDDO = 3.3V±5%, Outputs Unloaded
OE = 1, VDDO = 2.5V±5%, Outputs Unloaded
OE = 1, VDDO = 1.8V±0.15V, Outputs Unloaded
OE = 1, VDDO = 1.5V±0.1V, Outputs Unloaded
19 mA
3 mA
2 mA
2 mA
2 mA
REVISION 2 11/24/15
5 CRYSTAL OR DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK BUFFER
5 Page 
8L30210 DATA SHEET
Overdriving the XTAL Interface
The XTAL_IN input can be overdriven by an LVCMOS driver or by one
side of a differential driver through an AC coupling capacitor. The
XTAL_OUT pin can be left floating. The amplitude of the input signal
should be between 500mV and 1.8V and the slew rate should not be
less than 0.2V/nS. For 3.3V LVCMOS inputs, the amplitude must be
reduced from full swing to at least half the swing in order to prevent
signal interference with the power rail and to reduce internal noise.
Figure 4A shows an example of the interface diagram for a high
speed 3.3V LVCMOS driver. This configuration requires that the sum
of the output impedance of the driver (Ro) and the series resistance
(Rs) equals the transmission line impedance. In addition, matched
termination at the crystal input will attenuate the signal in half. This
can be done in one of two ways. First, R1 and R2 in parallel should
equal the transmission line impedance. For most 50 applications,
R1 and R2 can be 100. This can also be accomplished by removing
R1 and changing R2 to 50. The values of the resistors can be
increased to reduce the loading for a slower and weaker LVCMOS
driver. Figure4B shows an example of the interface diagram for an
LVPECL driver. This is a standard LVPECL termination with one side
of the driver feeding the XTAL_IN input. It is recommended that all
components in the schematics be placed in the layout. Though some
components might not be used, they can be utilized for debugging
purposes. The datasheet specifications are characterized and
guaranteed by using a quartz crystal as the input.
VCC
R1
100
Ro Rs Zo = 50 ohms
Zo = Ro + Rs
LVCMOS Driver
R2
100
XTAL_OUT
C1
XTAL_IN
.1uf
Figure 4A. General Diagram for LVCMOS Driver to XTAL Input Interface
XTAL_OUT
Zo = 50 ohms
Zo = 50 ohms
LVPECL Driver
R1
50
R2
50
R3
50
C2
XTAL_IN
.1uf
Figure 4B. General Diagram for LVPECL Driver to XTAL Input Interface
REVISION 2 11/24/15
11 CRYSTAL OR DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK BUFFER
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet 8L30210.PDF ] | |
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