PDF 87973I-147 Data sheet ( Hoja de datos )

Número de pieza	87973I-147
Descripción	1-to-12 LVCMOS/ LVTTL Clock Multiplier/ Zero Delay Buffer
Fabricantes	IDT
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No Preview Available ! Low Skew, 1-to-12 LVCMOS/ LVTTL Clock Multiplier/ Zero Delay Buffer 87973I-147 Data Sheet PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES MAY 6, 2017 General Description Features The 87973I-147 is a LVCMOS/LVTTL clock generator. The 87973I-147 has three selectable inputs and provides 14 LVCMOS/LVTTL outputs. The 87973I-147 is a highly flexible device. The three selectable inputs (1 differential and 2 single ended inputs) are often used in systems requiring redundant clock sources. Up to three different output frequencies can be generated among the three output banks. The three output banks and feedback output each have their own output dividers which allows the device to generate a multitude of different bank frequency ratios and output-to-input frequency ratios. In addition, 2 outputs in Bank C (QC2, QC3) can be selected to be inverting or non-inverting. The output frequency range is 10MHz to 150MHz. The input frequency range is 6MHz to 120MHz. The 87973I-147 also has a QSYNC output which can be used for system synchronization purposes. It monitors Bank A and Bank C outputs and goes low one period prior to coincident rising edges of Bank A and Bank C clocks. QSYNC then goes high again when the coincident rising edges of Bank A and Bank C occur. This feature is used primarily in applications where Bank A and Bank C are running at different frequencies, and is particularly useful when they are running at non-integer multiples of one another. Example Applications: 1.System Clock generator: Use a 16.66MHz reference clock to generate eight 33.33MHz copies for PCI and four 100MHz copies for the CPU or PCI-X. 2.Line Card Multiplier: Multiply differential 62.5MHz from a back plane to single-ended 125MHz for the line Card ASICs and Gigabit Ethernet Serdes. 3.Zero Delay buffer for Synchronous memory: Fanout up to twelve 100MHz copies from a memory controller reference clock to the memory chips on a memory module with zero delay. • Fully integrated PLL • Fourteen LVCMOS/LVTTL outputs to include: twelve clocks, one feedback, one sync • Selectable differential CLK, nCLK inputs or LVCMOS/LVTTL reference clock inputs • CLK0, CLK1 can accept the following input levels: LVCMOS or LVTTL • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Output frequency range: 10MHz to 150MHz • VCO range: 240MHz to 500MHz • Output skew: 200ps (maximum) • Cycle-to-cycle jitter, (all banks ÷4): 55ps (maximum) • Full 3.3V supply voltage • -40°C to 85°C ambient operating temperature • Compatible with PowerPC™and Pentium™Microprocessors • Available in lead-free packages • For drop-in replacement use 87973i Pin Assignment 39 38 37 36 35 34 33 32 31 30 29 28 27 FSEL_B1 40 26 FSEL_B0 41 25 FSEL_A1 42 24 FSEL_A0 43 23 QA3 44 22 VDDO 45 QA2 46 87973I-147 21 20 GNDO 47 19 QA1 48 18 VDDO 49 QA0 50 17 16 GNDO 51 15 VCO_SEL 52 14 1 2 3 4 5 6 7 8 9 10 11 12 13 FSEL_FB1 QSYNC GNDO QC0 VDDO QC1 FSEL_C0 FSEL_C1 QC2 VDDO QC3 GNDO INV_CLK 52-Lead, 10mm x 10mm LQFP ©2016 Integrated Device Technology, Inc 1 June 28, 2016 1 page 87973I-147 Data Sheet Table 2. Pin Characteristics Symbol Parameter CIN RPULLUP CPD Input Capacitance Input Pullup Resistor Power Dissipation Capacitance (per output) ROUT Output Impedance Test Conditions VDD, VDDA, VDDO = 3.465V Minimum Typical 4 51 57 Maximum 18 12 Units pF k pF  Function Tables Table 3A. Output Bank Configuration Select Function Table Inputs Outputs Inputs FSEL_A1 FSEL_A0 QA FSEL_B1 FSEL_B0 0 0 ÷4 0 0 0 1 ÷6 0 1 1 0 ÷8 1 0 1 1 ÷12 1 1 Outputs QB ÷4 ÷6 ÷8 ÷10 Inputs FSEL_C1 FSEL_C0 00 01 10 11 Outputs QC ÷2 ÷4 ÷6 ÷8 Table 3B. Feedback Configuration Select Function Table Inputs Outputs FSEL_FB2 FSEL_FB1 FSEL_FB0 QFB 000 ÷4 001 ÷6 010 ÷8 011 ÷10 100 ÷8 101 ÷12 110 ÷16 111 ÷20 Table 3C. Control Input Select Function Table Control Pin Logic 0 VCO_SEL VCO/2 REF_SEL CLK0 or CLK1 CLK_SEL CLK0 PLL_SEL BYPASS PLL nMR/OE Master Reset/Output High-Impedance INV_CLK Non-Inverted QC2, QC3 Logic 1 VCO XTAL CLK1 Enable PLL Enable Outputs Inverted QC2, QC3 ©2016 Integrated Device Technology, Inc 5 June 28, 2016 5 Page 87973I-147 Data Sheet Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The 87973I-147 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA and VDDO should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 2 illustrates this for a generic VDD pin and also shows that VDDA requires that an additional 10 resistor along with a 10F bypass capacitor be connected to the VDDA pin. VDD VDDA 3.3V 0.1µF Ferrite Bead 0.1µF 10µF Figure 2. Power Supply Filtering Wiring the Differential Input to Accept Single-Ended Levels Figure 3 shows how a differential input can be wired to accept single ended levels. The reference voltage V1= VDD/2 is generated by the bias resistors R1 and R2. The bypass capacitor (C1) is used to help filter noise on the DC bias. This bias circuit should be located as close to the input pin as possible. The ratio of R1 and R2 might need to be adjusted to position the V1in the center of the input voltage swing. For example, if the input clock swing is 2.5V and VDD = 3.3V, R1 and R2 value should be adjusted to set V1 at 1.25V. The values below are for when both the single ended swing and VDD are at the same voltage. This configuration requires that the sum of the output impedance of the driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the input will attenuate the signal in half. This can be done in one of two ways. First, R3 and R4 in parallel should equal the transmission line impedance. For most 50 applications, R3 and R4 can be 100. The values of the resistors can be increased to reduce the loading for slower and weaker LVCMOS driver. When using single-ended signaling, the noise rejection benefits of differential signaling are reduced. Even though the differential input can handle full rail LVCMOS signaling, it is recommended that the amplitude be reduced. The datasheet specifies a lower differential amplitude, however this only applies to differential signals. For single-ended applications, the swing can be larger, however VIL cannot be less than -0.3V and VIH cannot be more than VDD + 0.3V. Though some of the recommended components might not be used, the pads should be placed in the layout. They can be utilized for debugging purposes. The datasheet specifications are characterized and guaranteed by using a differential signal. Figure 3. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels ©2016 Integrated Device Technology, Inc 11 June 28, 2016 11 Page

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