83054 Datasheet PDF - IDT
Part Number | 83054 | |
Description | Single-Ended Multiplexer | |
Manufacturers | IDT | |
Logo | ||
There is a preview and 83054 download ( pdf file ) link at the bottom of this page. Total 14 Pages |
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83054
Data Sheet
GENERAL DESCRIPTION
The 83054 is a low skew, 4:1, Single-ended Multiplexer and a
member of the family of High Performance Clock Solutions from IDT.
The 83054 has four selectable single-ended clock inputs and one
single-ended clock output. The output has a V pin which may be
DDO
set at 3.3V, 2.5V, or 1.8V, making the device ideal for use in voltage
translation applications. An output enable pin places the output in
a high impedance state which may be useful for testing or
debug purposes. The device operates up to 250MHz and is pack-
aged in a 16 TSSOP package.
FEATURES
• 4:1 single-ended multiplexer
• Q nominal output impedance: 7Ω (V = 3.3V)
DDO
• Maximum output frequency: 250MHz
• Propagation delay: 3ns (maximum), V = V = 3.3V
DD DDO
• Input skew: 225ps (maximum), V = V = 3.3V
DD DDO
• Part-to-part skew: 780ps (maximum), V = V = 3.3V
DD DDO
• Additive phase jitter, RMS: 0.19ps (typical), 3.3V/3.3V
• Operating supply modes:
V /V
DD DDO
3.3V/3.3V
3.3V/2.5V
3.3V/1.8V
2.5V/2.5V
2.5V/1.8V
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
BLOCK DIAGRAM
CLK0
CLK1
CLK2
CLK3
SEL1
SEL0
OE
PIN ASSIGNMENT
Q
83054
16-Lead TSSOP
4.4mm x 5.0mm x 0.92mm package body
G Package
Top View
©2015 Integrated Device Technology, Inc
1
December 15, 2015
|
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83054 Data Sheet
TABLE 5B. AC CHARACTERISTICS, V = 3.3V ± 5%, V = 2.5V ± 5%, TA = -40°C TO 85°C
DD DDO
Symbol Parameter
Test Conditions
Minimum Typical Maximum
f
MAX
tp
LH
tp
HL
tsk(i)
Output Frequency
Propagation Delay, Low to High; NOTE 1
Propagation Delay, High to Low; NOTE 1
Input Skew; NOTE 2
250
2.5 2.8 3.1
2.6 2.8 3.0
45 150
Buffer Additive Phase Jitter, RMS;
tjit refer to Additive Phase Jitter Section;
NOTE 3
155.52MHz,
(12kHz to 20MHz)
0.14
tsk(pp) Part-to-Part Skew; NOTE 2, 4
780
t /t
RF
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
50
45
500
55
MUX MUX Isolation
ISOL
@ 100MHz
45
NOTE 1: Measured from V /2 of the input to V /2 of the output.
DD DDO
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Driving only one input clock.
NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at V /2.
DDO
Units
MHz
ns
ns
ps
ps
ps
ps
%
dB
TABLE 5C. AC CHARACTERISTICS, V = 3.3V ± 5%, V = 1.8V ± 5%, TA = -40°C TO 85°C
DD DDO
Symbol Parameter
Test Conditions
Minimum Typical Maximum
f
MAX
tp
LH
tp
HL
tsk(i)
Output Frequency
Propagation Delay, Low to High; NOTE 1
Propagation Delay, High to Low; NOTE 1
Input Skew; NOTE 2
250
2.7 3.2 3.8
2.8 3.3 3.8
50 150
Buffer Additive Phase Jitter, RMS;
tjit refer to Additive Phase Jitter Section;
NOTE 3
155.52MHz,
(12kHz to 20MHz)
0.16
tsk(pp) Part-to-Part Skew; NOTE 2, 4
780
t /t
RF
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
100
45
700
55
MUX MUX Isolation
ISOL
@ 100MHz
45
NOTE 1: Measured from V /2 of the input to V /2 of the output.
DD DDO
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Driving only one input clock.
NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at V /2.
DDO
Units
MHz
ns
ns
ps
ps
ps
ps
%
dB
©2015 Integrated Device Technology, Inc
5
December 15, 2015
Preview 5 Page |
Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for 83054 electronic component. |
Information | Total 14 Pages | |
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