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PDF 9ZXL1251 Data sheet ( Hoja de datos )
| Número de pieza | 9ZXL1251 | |
| Descripción | 12-output DB1200ZL Derivative | |
| Fabricantes | IDT | |
| Logotipo |  |
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12-output DB1200ZL Derivative with
Integrated 85Ω Terminations
9ZXL1251
DATASHEET
General Description
The 9ZXL1251 meets the demanding requirements of the
Intel DB1200ZL specification, including the critical low-drift
requirements of Intel CPUs. It is pin compatible to the
9ZXL1231 and integrates 24 termination resistors, saving
41mm2 board area.
Recommended Application
Buffer for Romley, Grantley and Purley Servers, solid state
storage and PCIe
Output Features
• 12 LP-HCSL Output Pairs w/integrated terminations (Zo =
85Ω)
Key Specifications
• Cycle-to-cycle jitter <50ps
• Output-to-output skew <50ps
• Input-to-output delay variation <50ps
• PCIe Gen3 phase jitter <1.0ps RMS
• Phase jitter: QPI/UPI >=9.6GB/s <0.2ps rms
Features/Benefits
• 85Ω Low-power push-pull HCSL outputs; eliminate 24
resistors, save 41mm2 of area
• Pin compatible to 9ZX21201 and 9ZXL1231; easy path to
power and area savings
• Space-saving 64-pin VFQFPN package
• Fixed feedback path for 0ps input-to-output delay
• 9 Selectable SMBus Addresses; multiple devices can
share the same SMBus Segment
• 12 OE# pins; hardware control of each output
• PLL or bypass mode; supports common and separate clock
architectures
• Selectable PLL bandwidth; minimizes jitter peaking in
downstream PLL's
• Spread Spectrum Compatible; tracks spreading input clock
for low EMI
• -40°C to +85°C device available; supports demanding
environmental applications
Block Diagram
OE(11:0)#
DIF_IN
DIF_IN#
Z-PLL
(SS Compatible)
DFB_OUT_NC
DIF(11:0)
HIBW_BYPM_LOBW#
100M_133M#
CKPWRGD/PD#
SMB_A0_tri
SMB_A1_tri
SMBDAT
SMBCLK
Logic
9ZXL1251 REVISION B 11/20/15 1 ©2015 Integrated Device Technology, Inc.
1 page  
9ZXL1251 DATASHEET
Pin Descriptions (cont.)
PIN #
PIN NAME
38 DIF_5
39 DIF_5#
40 VDD
41 GND
42 DIF_6
43 DIF_6#
TYPE
OUT
OUT
PWR
GND
OUT
OUT
44 vOE6#
IN
45 vOE7#
46 DIF_7
47 DIF_7#
48 GND
49 VDDIO
50 DIF_8
51 DIF_8#
52 vOE8#
IN
OUT
OUT
GND
PWR
OUT
OUT
IN
53 vOE9#
54 DIF_9
55 DIF_9#
56 VDDIO
57 VDD
58 GND
59 DIF_10
60 DIF_10#
61 vOE10#
IN
OUT
OUT
PWR
PWR
GND
OUT
OUT
IN
62 vOE11#
63 DIF_11
64 DIF_11#
65 epad
IN
OUT
OUT
GND
DESCRIPTION
HCSL true clock output
HCSL Complementary clock output
Power supply, nominal 3.3V
Ground pin.
HCSL true clock output
HCSL Complementary clock output
Active low input for enabling DIF pair 6. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Active low input for enabling DIF pair 7. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
HCSL true clock output
HCSL Complementary clock output
Ground pin.
Power supply for differential outputs
HCSL true clock output
HCSL Complementary clock output
Active low input for enabling DIF pair 8. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Active low input for enabling DIF pair 9. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
HCSL true clock output
HCSL Complementary clock output
Power supply for differential outputs
Power supply, nominal 3.3V
Ground pin.
HCSL true clock output
HCSL Complementary clock output
Active low input for enabling DIF pair 10. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Active low input for enabling DIF pair 11. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
HCSL true clock output
HCSL Complementary clock output
epad, connect to ground
REVISION B 11/20/15
5 12-OUTPUT DB1200ZL DERIVATIVE WITH INTEGRATED 85Ω TERMINATIONS
5 Page 
9ZXL1251 DATASHEET
Clock Periods–Differential Outputs with Spread Spectrum Disabled
SSC OFF
DIF
Center
Freq.
MHz
100.00
133.33
1 Clock
-c2c jitter
AbsPer
Min
9.94900
7.44925
1us
-SSC
Short-Term
Average
Min
Measurement Window
0.1s 0.1s
0.1s
- ppm
Long-Term
Average
Min
0 ppm
Period
Nominal
+ ppm
Long-Term
Average
Max
9.99900 10.00000
10.00100
7.49925
7.50000
7.50075
1us
+SSC
Short-Term
Average
Max
1 Clock
+c2c jitter
AbsPer
Max
10.05100
7.55075
Units Notes
ns 1,2,3
ns 1,2,4
Clock Periods–Differential Outputs with Spread Spectrum Enabled
Measurement Window
SSC ON
Center
Freq.
MHz
1 Clock
1us
0.1s
-c2c jitter
AbsPer
Min
-SSC
Short-Term
Average
Min
- ppm
Long-Term
Average
Min
0.1s
0 ppm
Period
Nominal
0.1s
+ ppm
Long-Term
Average
Max
1us
+SSC
Short-Term
Average
Max
1 Clock
+c2c jitter
AbsPer
Max
Units
DIF 99.75 9.94906 9.99906 10.02406 10.02506
133.00 7.44930 7.49930
7.51805
7.51880
10.02607
7.51955
10.05107
7.53830
10.10107
7.58830
ns
ns
Notes:
1Guaranteed by design and characterization, not 100% tested in production.
2 All Long Term Accuracy specifications are guaranteed with the assumption that the input clock complies with CK420BQ/CK410B+
accuracy requirements (+/-100ppm). The 9ZXL1251 itself does not contribute to ppm error.
3 Driven by SRC output of main clock, 100 MHz PLL Mode or Bypass mode
4 Driven by CPU output of main clock, 133 MHz PLL Mode or Bypass mode
Notes
1,2,3
1,2,4
Differential Output Terminations
DIF Zo (Ω)
Rs (Ω)
100 NA
85 0
Low-Power
HCSL Output
buffer w/internal
termination
10 inches
85ohm Differential Zo
2pF 2pF
REVISION B 11/20/15
11 12-OUTPUT DB1200ZL DERIVATIVE WITH INTEGRATED 85Ω TERMINATIONS
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet 9ZXL1251.PDF ] | |
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