9DBV0831 Datasheet PDF - IDT
Part Number | 9DBV0831 | |
Description | 8-output 1.8V PCIe Gen1/2/3 Zero-Delay/Fan-out Buffer | |
Manufacturers | IDT | |
Logo | ||
There is a preview and 9DBV0831 download ( pdf file ) link at the bottom of this page. Total 19 Pages |
Preview 1 page No Preview Available ! 8-output 1.8V PCIe Gen1/2/3
Zero-Delay/Fan-out Buffer (ZDB/FOB)
9DBV0831
DATASHEET
Description
The 9DBV0831 is a member of IDT's SOC-Friendly 1.8V
Very-Low-Power (VLP) PCIe family. It can also be used for
50M or 125M Ethernet Applications via software frequency
selection. The device has 8 output enables for clock
management, and 3 selectable SMBus addresses.
Recommended Application
1.8V PCIe Gen1-2-3 Zero-Delay/Fan-out Buffer (ZDB/FOB)
Output Features
• 8 – 1-200Hz Low-Power (LP) HCSL DIF pairs
w/ZO=100ohms
Key Specifications
• DIF cycle-to-cycle jitter <50ps
• DIF output-to-output skew <50ps
• DIF additive phase jitter is <100fs rms for PCIe Gen3
• DIF additive phase jitter <300fs rms for 12k-20MHz
Block Diagram
Features/Benefits
• LP-HCSL outputs save 16 resistors; minimal board space
and BOM cost
• 62mW typical power consumption in PLL mode; minimal
power consumption
• Spread Spectrum (SS) compatible; allows use of SS for
EMI reduction
• OE# pins; support DIF power management
• HCSL compatible differential input; can be driven by
common clock sources
• Programmable Slew rate for each output; allows tuning for
various line lengths
• Programmable output amplitude; allows tuning for various
application environments
• Pin/software selectable PLL bandwidth and PLL Bypass;
minimize phase jitter for each application
• Outputs blocked until PLL is locked; clean system start-up
• Software selectable 50MHz or 125MHz PLL operation;
useful for Ethernet applications
• Configuration can be accomplished with strapping pins;
SMBus interface not required for device control
• 3.3V tolerant SMBus interface works with legacy controllers
• Space saving 48-pin 6x6mm VFQFPN; minimal board
space
• Selectable SMBus addresses; multiple devices can easily
share an SMBus segment
vOE(7:0)#
8
CLK_IN
CLK_IN#
vSADR
^vHIBW_BYPM_LOBW#
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
SS-
Compatible
PLL
CONTROL
LOGIC
DIF7
DIF6
DIF5
DIF4
DIF3
DIF2
DIF1
DIF0
9DBV0831 REVISION H 04/28/16 1 ©2016 Integrated Device Technology, Inc.
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9DBV0831 DATASHEET
Pin Descriptions (cont.)
PIN #
PIN NAME
39 VDDIO
40 GND
41 DIF6
42 DIF6#
TYPE
PWR
GND
OUT
OUT
43 vOE6#
IN
44 DIF7
45 DIF7#
OUT
OUT
46 vOE7#
IN
47 VDDIO
PWR
48 ^CKPWRGD_PD#
IN
49 EPAD
GND
DESCRIPTION
Power supply for differential outputs
Ground pin.
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 6. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 7. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Power supply for differential outputs
Input notifies device to sample latched inputs and start up on first high
assertion. Low enters Power Down Mode, subsequent high assertions exit
Power Down Mode. This pin has internal pull-up resistor.
Connect to Ground
REVISION H 04/28/16
5 8-OUTPUT 1.8V PCIE GEN1/2/3 ZERO-DELAY/FAN-OUT BUFFER (ZDB/FOB)
Preview 5 Page |
Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for 9DBV0831 electronic component. |
Information | Total 19 Pages | |
Link URL | [ Copy URL to Clipboard ] | |
Download | [ 9DBV0831.PDF Datasheet ] |
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