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PDF 9DBV0241 Data sheet ( Hoja de datos )
| Número de pieza | 9DBV0241 | |
| Descripción | 2-Output 1.8V PCIe Gen1-2-3 Zero Delay / Fanout Buffer | |
| Fabricantes | IDT | |
| Logotipo |  |
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2-Output 1.8V PCIe Gen1-2-3 Zero Delay /
Fanout Buffer with Zo=100ohms
9DBV0241
DATASHEET
Description
The 9DBV0241 is a member of IDT's 1.8V Very-Low-Power
(VLP) PCIe family. The device has 2 output enables for clock
management.
Recommended Application
1.8V PCIe Gen1/2/3 Zero-Delay/Fan-out Buffer (ZDB/FOB)
Output Features
• 2 - 0.7V low-power HCSL-compatible (LP-HCSL) DIF pairs
w/ZO=100
Key Specifications
• DIF cycle-to-cycle jitter <50ps
• DIF output-to-output skew <50ps
• DIF additive phase jitter is <100fs rms for PCIe Gen3
• DIF additive phase jitter <300fs rms (12k-20MHz)
Block Diagram
Features/Benefits
• LP-HCSL outputs with Zo=100; saves 8 resistors
compared to standard HCSL output
• 35mW typical power consumption in PLL mode; minimal
power consumption
• Spread Spectrum (SS) compatible; allows use of SS for
EMI reduction
• OE# pins; support DIF power management
• HCSL compatible differential input; can be driven by
common clock sources
• SMBus-selectable features; optimize signal integrity to
application
• slew rate for each output
• differential output amplitude
• Pin/software selectable PLL bandwidth and PLL Bypass;
optimize PLL to application
• Outputs blocked until PLL is locked; clean system start-up
• Device contains default configuration; SMBus interface not
required for device control
• 3.3V tolerant SMBus interface; works with legacy
controllers
• Space saving 24-pin 4x4mm VFQFPN; minimal board
space
vOE(1:0)#
2
CLK_IN
CLK_IN#
SS-
Compatible
PLL
DIF1
DIF0
^vHIBW_BYPM_LOBW#
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
CONTROL
LOGIC
9DBV0241 REVISION D 09/11/15 1 ©2015 Integrated Device Technology, Inc.
1 page  
9DBV0241 DATASHEET
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 9DBV0241. These ratings, which are standard
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the
recommended operating temperature range.
PARAMETER
SYMBOL
CONDITIONS
1.8V Supply Voltage
VDDxx
Applies to all VDD pins
Input Voltage
VIN
Input High Voltage, SMBus VIHSMB
Storage Temperature
Ts
SMBus clock and data pins
Junction Temperature
Tj
Input ESD protection ESD prot
Human Body Model
1Guaranteed by design and characterization, not 100% tested in production.
2 Operation under these conditions is neither implied nor guaranteed.
3 Not to exceed 2.5V.
MIN
-0.5
-0.5
-65
2000
TYP
MAX
2.5
VDD+0.5V
3.6V
150
125
UNITS
V
V
V
°C
°C
V
NOTES
1,2
1, 3
1
1
1
1
Electrical Characteristics–Clock Input Parameters
TA = TCOM or TIND; Supply Voltage per VDD of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN TYP
Input Common Mode
Voltage - DIF_IN
Input Swing - DIF_IN
Input Slew Rate - DIF_IN
VCOM
VSWING
dv/dt
Common Mode Input Voltage
Differential value
Measured differentially
150
300
0.4
Input Leakage Current
Input Duty Cycle
IIN
dtin
VIN = VDD , VIN = GND
Measurement from differential wavefrom
-5
45
Input Jitter - Cycle to Cycle JDIFIn
Differential Measurement
1 Guaranteed by design and characterization, not 100% tested in production.
2Slew rate measured through +/-75mV window centered around differential zero
0
MAX
1000
1450
8
5
55
125
UNITS NOTES
mV 1
mV
V/ns
uA
%
ps
1
1,2
1
1
REVISION D 09/11/15
5
2-OUTPUT 1.8V PCIE GEN1-2-3 ZERO DELAY / FANOUT BUFFER WITH ZO=100OHMS
5 Page 
9DBV0241 DATASHEET
SMBus Table: Output Enable Register 1
Byte 0
Name
Control Function
Type
0
Bit 7
Reserved
Bit 6
Reserved
Bit 5
DIF OE1
Output Enable
RW Low/Low
Bit 4
Reserved
Bit 3
DIF OE0
Output Enable
RW Low/Low
Bit 2
Reserved
Bit 1
Reserved
Bit 0
Reserved
1. A low on these bits will overide the OE# pin and force the differential output Low/Low
1
Enabled
Enabled
Default
1
1
1
1
1
1
1
1
SMBus Table: PLL Operating Mode and Output Amplitude Control Register
Byte 1
Bit 7
Bit 6
Bit 5
Name
PLLMODERB1
PLLMODERB0
PLLMODE_SWCNTRL
Control Function
PLL Mode Readback Bit 1
PLL Mode Readback Bit 0
Type
R
R
Enable SW control of PLL Mode RW
01
See PLL Operating Mode Table
Values in B1[7:6] Values in B1[4:3]
set PLL Mode
set PLL Mode
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PLLMODE1
PLLMODE0
AMPLITUDE 1
AMPLITUDE 0
PLL Mode Control Bit 1
PLL Mode Control Bit 0
Reserved
Controls Output Amplitude
RW1
RW1
RW
RW
See PLL Operating Mode Table
00 = 0.6V
10= 0.8V
01 = 0.7V
11 = 0.9V
1. B1[5] must be set to a 1 for these bits to have any effect on the part.
Default
Latch
Latch
0
0
0
1
1
0
SMBus Table: DIF Slew Rate Control Register
Byte 2
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
SLEWRATESEL DIF1
SLEWRATESEL DIF0
Control Function
Reserved
Reserved
Slew Rate Selection
Reserved
Slew Rate Selection
Reserved
Reserved
Reserved
Type
RW
RW
0
2 V/ns
2 V/ns
1
3 V/ns
3 V/ns
Default
1
1
1
1
1
1
1
1
SMBus Table: Frequency Select Control Register
Byte 3
Name
Control Function
Bit 7
Bit 6
Bit 5
FREQ_SEL_EN
Reserved
Reserved
Enable SW selection of
frequency
Bit 4
FSEL1
Freq. Select Bit 1
Bit 3
FSEL0
Freq. Select Bit 0
Bit 2
Bit 1
Bit 0
SLEWRATESEL FB
Reserved
Reserved
Adjust Slew Rate of FB
1. B3[5] must be set to a 1 for these bits to have any effect on the part.
Type
RW
RW1
RW1
RW
01
SW frequency
change disabled
SW frequency
change enabled
See Frequency Select Table
2 V/ns
3 V/ns
Default
1
1
0
0
0
1
1
1
Byte 4 is Reserved and reads back 'hFF
REVISION D 09/11/15
11
2-OUTPUT 1.8V PCIE GEN1-2-3 ZERO DELAY / FANOUT BUFFER WITH ZO=100OHMS
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet 9DBV0241.PDF ] | |
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