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What is 9DBV0241?

This electronic component, produced by the manufacturer "IDT", performs the same function as "2-Output 1.8V PCIe Gen1-2-3 Zero Delay / Fanout Buffer".


9DBV0241 Datasheet PDF - IDT

Part Number 9DBV0241
Description 2-Output 1.8V PCIe Gen1-2-3 Zero Delay / Fanout Buffer
Manufacturers IDT 
Logo IDT Logo 


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2-Output 1.8V PCIe Gen1-2-3 Zero Delay /
Fanout Buffer with Zo=100ohms
9DBV0241
DATASHEET
Description
The 9DBV0241 is a member of IDT's 1.8V Very-Low-Power
(VLP) PCIe family. The device has 2 output enables for clock
management.
Recommended Application
1.8V PCIe Gen1/2/3 Zero-Delay/Fan-out Buffer (ZDB/FOB)
Output Features
2 - 0.7V low-power HCSL-compatible (LP-HCSL) DIF pairs
w/ZO=100
Key Specifications
DIF cycle-to-cycle jitter <50ps
DIF output-to-output skew <50ps
DIF additive phase jitter is <100fs rms for PCIe Gen3
DIF additive phase jitter <300fs rms (12k-20MHz)
Block Diagram
Features/Benefits
LP-HCSL outputs with Zo=100; saves 8 resistors
compared to standard HCSL output
35mW typical power consumption in PLL mode; minimal
power consumption
Spread Spectrum (SS) compatible; allows use of SS for
EMI reduction
OE# pins; support DIF power management
HCSL compatible differential input; can be driven by
common clock sources
SMBus-selectable features; optimize signal integrity to
application
slew rate for each output
differential output amplitude
Pin/software selectable PLL bandwidth and PLL Bypass;
optimize PLL to application
Outputs blocked until PLL is locked; clean system start-up
Device contains default configuration; SMBus interface not
required for device control
3.3V tolerant SMBus interface; works with legacy
controllers
Space saving 24-pin 4x4mm VFQFPN; minimal board
space
vOE(1:0)#
2
CLK_IN
CLK_IN#
SS-
Compatible
PLL
DIF1
DIF0
^vHIBW_BYPM_LOBW#
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
CONTROL
LOGIC
9DBV0241 REVISION D 09/11/15 1 ©2015 Integrated Device Technology, Inc.

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9DBV0241 equivalent
9DBV0241 DATASHEET
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 9DBV0241. These ratings, which are standard
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the
recommended operating temperature range.
PARAMETER
SYMBOL
CONDITIONS
1.8V Supply Voltage
VDDxx
Applies to all VDD pins
Input Voltage
VIN
Input High Voltage, SMBus VIHSMB
Storage Temperature
Ts
SMBus clock and data pins
Junction Temperature
Tj
Input ESD protection ESD prot
Human Body Model
1Guaranteed by design and characterization, not 100% tested in production.
2 Operation under these conditions is neither implied nor guaranteed.
3 Not to exceed 2.5V.
MIN
-0.5
-0.5
-65
2000
TYP
MAX
2.5
VDD+0.5V
3.6V
150
125
UNITS
V
V
V
°C
°C
V
NOTES
1,2
1, 3
1
1
1
1
Electrical Characteristics–Clock Input Parameters
TA = TCOM or TIND; Supply Voltage per VDD of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN TYP
Input Common Mode
Voltage - DIF_IN
Input Swing - DIF_IN
Input Slew Rate - DIF_IN
VCOM
VSWING
dv/dt
Common Mode Input Voltage
Differential value
Measured differentially
150
300
0.4
Input Leakage Current
Input Duty Cycle
IIN
dtin
VIN = VDD , VIN = GND
Measurement from differential wavefrom
-5
45
Input Jitter - Cycle to Cycle JDIFIn
Differential Measurement
1 Guaranteed by design and characterization, not 100% tested in production.
2Slew rate measured through +/-75mV window centered around differential zero
0
MAX
1000
1450
8
5
55
125
UNITS NOTES
mV 1
mV
V/ns
uA
%
ps
1
1,2
1
1
REVISION D 09/11/15
5
2-OUTPUT 1.8V PCIE GEN1-2-3 ZERO DELAY / FANOUT BUFFER WITH ZO=100OHMS


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Part Details

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Featured Datasheets

Part NumberDescriptionMFRS
9DBV0241The function is 2-Output 1.8V PCIe Gen1-2-3 Zero Delay / Fanout Buffer. IDTIDT

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