9DBU0841 Datasheet PDF - IDT
Part Number | 9DBU0841 | |
Description | 8 O/P 1.5V PCIe Gen1-2-3 ZDB/FOB | |
Manufacturers | IDT | |
Logo | ||
There is a preview and 9DBU0841 download ( pdf file ) link at the bottom of this page. Total 17 Pages |
Preview 1 page No Preview Available ! 8 O/P 1.5V PCIe Gen1-2-3 ZDB/FOB
w/Zo=100ohms
9DBU0841
DATASHEET
Description
The 9DBU0841 is a member of IDT's 1.5V Ultra-Low-Power
(ULP) PCIe family. It has integrated output terminations
providing Zo=100 for direct connection to 100
transmission lines. The device has 8 output enables for clock
management and 3 selectable SMBus addresses.
Recommended Application
1.5V PCIe Gen1-2-3 Zero Delay/Fanout Buffer (ZDB/FOB)
Output Features
• 8 – 1-167MHz Low-Power (LP) HCSL DIF pairs
w/ZO=100
Key Specifications
• DIF cycle-to-cycle jitter <50ps
• DIF output-to-output skew < 80ps
• DIF phase jitter is PCIe Gen1-2-3 compliant
• Very low additive phase jitter in bypass mode
Block Diagram
Features/Benefits
• Direct connection to 100 transmission lines; saves 32
resistors compared to standard HCSL outputs
• 53mW typical power consumption in PLL mode; eliminates
thermal concerns
• Outputs can optionally be supplied from any voltage
between 1.05 and 1.5V; maximum power savings
• Spread Spectrum (SS) compatible; allows SS for EMI
reduction
• OE# pins; support DIF power management
• HCSL-compatible differential input; can be driven by
common clock sources
• Spread Spectrum tolerant; allows reduction of EMI
• SMBus-selectable features; optimize signal integrity to
application
• slew rate for each output
• differential output amplitude
• Pin/SMBus selectable PLL bandwidth and PLL Bypass;
optimize PLL to application
• Outputs blocked until PLL is locked; clean system start-up
• Device contains default configuration; SMBus interface not
required for device control
• Three selectable SMBus addresses; multiple devices can
easily share an SMBus segment
• 3.3V tolerant SMBus interface works with legacy controllers
• Space saving 48-pin 6x6mm VFQFPN; minimal board
space
vOE(7:0)#
8
CLK_IN
CLK_IN#
vSADR
^vHIBW_BYPM_LOBW#
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
SS-
Compatible
PLL
CONTROL
LOGIC
DIF7
DIF6
DIF5
DIF4
DIF3
DIF2
DIF1
DIF0
9DBU0841 REVISION C 04/22/15
1
©2015 Integrated Device Technology, Inc.
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9DBU0841 DATASHEET
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 9DBU0841. These ratings, which are standard
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the
recommended operating temperature range.
PARAMETER
SYMBOL
CONDITIONS
Supply Voltage
VDDx
Input Voltage
VIN
Input High Voltage, SMBus VIHSMB
Storage Temperature
Ts
SMBus clock and data pins
Junction Temperature
Tj
Input ESD protection
ESD prot
Human Body Model
1Guaranteed by design and characterization, not 100% tested in production.
2 Operation under these conditions is neither implied nor guaranteed.
3 Not to exceed 2.0V.
MIN
-0.5
-0.5
-65
2000
TYP
MAX
2
VDD+0.5
3.3
150
125
UNITS NOTES
V 1,2
V 1,3
V1
°C 1
°C 1
V1
Electrical Characteristics–Clock Input Parameters
TA = TAMB, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
Input Common Mode
Voltage - DIF_IN
VCOM
Common Mode Input Voltage
200
Input Swing - DIF_IN
Input Slew Rate - DIF_IN
VSWING
dv/dt
Differential value
Measured differentially
300
0.4
Input Leakage Current
IIN
VIN = VDD , VIN = GND
Input Duty Cycle dtin Measurement from differential wavefrom
Input Jitter - Cycle to Cycle JDIFIn
Differential Measurement
1 Guaranteed by design and characterization, not 100% tested in production.
2 Slew rate measured through +/-75mV window centered around differential zero
-5
45
0
TYP
50
MAX
725
1450
8
5
55
150
UNITS NOTES
mV 1
mV
V/ns
uA
%
ps
1
1,2
1
1
REVISION C 04/22/15
5 8 O/P 1.5V PCIE GEN1-2-3 ZDB/FOB W/ZO=100OHMS
Preview 5 Page |
Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for 9DBU0841 electronic component. |
Information | Total 17 Pages | |
Link URL | [ Copy URL to Clipboard ] | |
Product Image and Detail view | 1. - PCIe Zero-Delay/Fanout Clock Buffer [ Learn More ] | |
Download | [ 9DBU0841.PDF Datasheet ] |
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