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What is 9DB433?

This electronic component, produced by the manufacturer "IDT", performs the same function as "FOUR OUTPUT DIFFERENTIAL BUFFER".


9DB433 Datasheet PDF - IDT

Part Number 9DB433
Description FOUR OUTPUT DIFFERENTIAL BUFFER
Manufacturers IDT 
Logo IDT Logo 


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FOUR OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1,2,3
DATASHEET
9DB433
General Description
The 9DB433 zero-delay buffer supports PCIe Gen3
requirements, while being backwards compatible to PCIe
Gen2 and Gen1. The 9DB433 is driven by a differential
SRC output pair from an IDT 932S421 or 932SQ420 or
equivalent main clock generator.
Recommended Application
4 output PCIe Gen1,2,3 zero-delay/fanout buffer
Key Specifications
Output cycle-cycle jitter <50ps
Output to Output skew <50ps
Phase jitter: PCIe Gen3 <1.0ps rms
Functional Block Diagram
OE(6,1)#
2
Features/Benefits
3 Selectable SMBus Addresses; Mulitple devices can
share the same SMBus Segment
OE# pins; Suitable for Express Card applications
PLL or bypass mode; PLL can dejitter incoming clock
Selectable PLL bandwidth; minimizes jitter peaking in
downstream PLL's
Spread Spectrum Compatible; tracks spreading input
clock for low EMI
SMBus Interface; unused outputs can be disabled
Supports undriven differential outputs in Power Down
mode for power management
Output Features
4 - 0.7V current-mode differential HCSL output pairs
Supports zero delay buffer mode and fanout mode
Selectable bandwidth
50-110 MHz operation in PLL mode
5-166 MHz operation in Bypass mode
SRC_IN
SRC_IN#
SPREAD
COMPATIBLE
PLL
M
U
X
STOP
LOGIC
4
DIF(6,5,2,1)
PD#
BYP#_LOBW_HIBW
SMBDAT
SMBCLK
CONTROL
LOGIC
IREF
IDT® FOUR OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1,2,3
1
9DB433
REV G 08/25/15

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9DB433 equivalent
9DB433
FOUR OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1,2,3
Electrical Characteristics–Input/Supply/Common Parameters
TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
Ambient Operating
Temperature
Input High Voltage
Input Low Voltage
TCOM
TIND
VIH
VIL
IIN
Commmercial range
Industrial range
Single-ended inputs, except SMBus, low
threshold and tri-level inputs
Single-ended inputs, except SMBus, low
threshold and tri-level inputs
Single-ended inputs, VIN = GND, VIN = VDD
0
-40
2
GND - 0.3
-5
Input Current
Single-ended inputs
IINP
VIN = 0 V; Inputs with internal pull-up resistors
-200
VIN = VDD; Inputs with internal pull-down resistors
Input Frequency
Pin Inductance
Capacitance
Clk Stabilization
Fibyp
Fipll
Lpin
CIN
CINDIF_IN
COUT
TSTAB
VDD = 3.3 V, Bypass mode
VDD = 3.3 V, 100MHz PLL mode
Logic Inputs, except DIF_IN
DIF_IN differential clock inputs
Output pin capacitance
From VDD Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
5
50
1.5
1.5
TYP
-0.02
100
MAX
70
85
UNITS NOTES
°C 1
°C 1
VDD + 0.3 V
1
0.8 V 1
5 uA 1
200 uA 1
166 MHz 2
110 MHz 2
7 nH 1
5 pF 1
2.7 pF 1,4
6 pF 1
1 ms 1,2
Input SS Modulation
Frequency
fMODIN
Allowable Frequency
(Triangular Modulation)
30 31.5 33 kHz 1
OE# Latency
Tdrive_PD#
tLATOE#
tDRVPD
DIF start after OE# assertion
DIF stop after OE# deassertion
DIF output enable after
PD# de-assertion
Tfall tF Fall time of control inputs
Trise tR Rise time of control inputs
SMBus Input Low Voltage VILSMB
SMBus Input High Voltage VIHSMB
SMBus Output Low Voltage VOLSMB
@ IPULLUP
SMBus Sink Current
IPULLUP
@ VOL
Nominal Bus Voltage
VDDSMB
3V to 5V +/- 10%
SCLK/SDATA Rise Time
tRSMB
(Max VIL - 0.15) to (Min VIH + 0.15)
SCLK/SDATA Fall Time
tFSMB
(Min VIH + 0.15) to (Max VIL - 0.15)
SMBus Operating
Frequency
fMAXSMB
Maximum SMBus operating frequency
1Guaranteed by design and characterization, not 100% tested in production.
2Control input must be monotonic from 20% to 80% of input swing.
3Time from deassertion until outputs are >200 mV
4DIF_IN input
5The differential input clock must be running for the SMBus to be active
1 2 3 cycles 1,3
13 300 us 1,3
5 ns 1,2
5 ns 1,2
0.8 V 1
2.1
VDDSMB
V
1
0.4 V 1
4 mA 1
2.7 5.5 V 1
1000
ns
1
300 ns 1
100 kHz 1,5
IDT® FOUR OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1,2,3
5
9DB433
REV G 08/25/15


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