PDF 9DB1904B Data sheet ( Hoja de datos )

Número de pieza	9DB1904B
Descripción	19 Output Differential Buffer
Fabricantes	IDT
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No Preview Available ! Datasheet 19 Output Differential Buffer for PCIe Gen2 and QPI 9DB1904B Description The 9DB1904 is electrically compatible to the Intel DB1900GS Differential Buffer Specification.This buffer provides 19 output clocks for PCI-Express Gen2 or Intel QPI 6.4GT/s applications. A differential clock from a CK410B+ main clock generator, such as the ICS932S421 drives the 9DB1904. The 9DB1904 can provide outputs up to 400MHz in Bypass Mode. Recommended Application 19 Output Differential Buffer for PCIe Gen2 and QPI Key Specifications • DIF output cycle-to-cycle jitter < 50ps • DIF output-to-output skew < 150ps across all outputs Features/Benefits • Power up default is all outputs in 1:1 mode/No SMBus programming • Spread spectrum compatible/EMI reductions • Supports output frequencies up to 400 MHz in bypass mode/flexible fanout buffer • 8 Selectable SMBus addresses/no SMBus segmentation required • SMBus address determines PLL or Bypass mode/pin savings • Dedicated VDDA and CKPWRGD_PD# pins/easy board design Functionality at Power Up (PLL Mode) 100M_133M# CLK_IN MHz 1 100MHz 0 133MHz Pin Configuration DIF_(18:0) MHz CLK_IN CLK_IN Power Down Functionality INPUTS CKPWRGD_ CLK_IN/ PD# CLK_IN# 1 Running 0X OUTPUTS DIF/DIF# Running Hi-Z PLL State ON OFF 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 IREF 1 GNDA 2 VDDA 3 HIGH_BW# 4 100M_133M#_LV 5 DIF_0 6 DIF_0# 7 DIF_1 8 DIF_1# 9 GND 10 9DB1904BKLF VDD 11 DIF_2 12 DIF_2# 13 DIF_3 14 DIF_3# 15 DIF_4 16 DIF_4# 17 OE_01234# 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 54 OE14# 53 DIF_13# 52 DIF_13 51 OE13# 50 DIF_12# 49 DIF_12 48 OE12# 47 VDD 46 GND 45 DIF_11# 44 DIF_11 43 OE11# 42 DIF_10# 41 DIF_10 40 OE10# 39 DIF_9# 38 DIF_9 37 OE9# IDT® 19 Output Differential Buffer for PCIe Gen2 and QPI 1 1607C —04/19/11 1 page 9DB1904B 19 Output Differential Buffer for PCIe Gen2 and QPI Electrical Characteristics - Absolute Maximum Ratings PARAMETER SYMBOL CONDITIONS 3.3V Core Supply Voltage VDDA 3.3V Logic Supply Voltage VDD Input Low Voltage VIL Input High Voltage VIH Except for SMBus interface Input High Voltage VIHSMB SMBus clock and data pins Storage Temperature Ts Junction Temperature Tj Input ESD protection ESD prot Human Body Model 1Guaranteed by design and characterization, not 100% tested in production. 2 Operation under these conditions is neither implied nor guaranteed. MIN GND-0.5 -65 2000 TYP MAX UNITS NOTES 4.6 V 1,2 4.6 V 1,2 V1 VDD+0.5V 5.5V V V 1 1 150 °C 1 125 °C 1 V1 Electrical Characteristics - Clock Input Parameters TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions PARAMETER SYMBOL CONDITIONS MIN TYP Input High Voltage - DIF_IN VIHDIF Differential inputs (single-ended measurement) 600 800 Input Low Voltage - DIF_IN VILDIF Differential inputs (single-ended measurement) VSS - 300 0 Input Common Mode Voltage - DIF_IN VCOM Common Mode Input Voltage 300 Input Amplitude - DIF_IN Input Slew Rate - DIF_IN VSWING dv/dt Peak to Peak value Measured differentially 300 0.4 Input Leakage Current IIN VIN = VDD , VIN = GND -5 Input Duty Cycle dtin Measurement from differential wavefrom 45 Input Jitter - Cycle to Cycle JDIFIn Differential Measurement 1 Guaranteed by design and characterization, not 100% tested in production. 0 2Slew rate measured through +/-75mV window centered around differential zero 3 Input duty cycle will directly impact output duty cycle in bypass mode. It has no impact in PLL mode. MAX 1150 UNITS NOTES mV 1 300 mV 1 1000 1450 8 5 55 125 mV mV V/ns uA % ps 1 1 1,2 1 1, 3 1 Electrical Characteristics - Current Consumption TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions PARAMETER SYMBOL CONDITIONS MIN Operating Supply Current IDD3.3OP IDD3.3AOP VDD, All outputs active @100MHz VDDA, All outputs active @100MHz Powerdown Current IDD3.3PD IDD3.3APD VDD VDDA 1Guaranteed by design and characterization, not 100% tested in production. Zo = 100Ω TYP 425 35 20 12 MAX 450 45 25 15 UNITS mA mA mA mA NOTES 1 1 1 1 IDT® 19 Output Differential Buffer for PCIe Gen2 and QPI 5 1607C—04/19/11 5 Page 9DB1904B 19 Output Differential Buffer for PCIe Gen2 and QPI Alternative Termination for LVDS and other Common Differential Signals (figure 3) Vdiff Vp-p Vcm R1 R2 R3 R4 Note 0.45v 0.22v 1.08 33 150 100 100 0.58 0.28 0.6 33 78.7 137 100 0.80 0.40 0.6 33 78.7 none 100 ICS874003i-02 input compatible 0.60 0.3 1.2 33 174 140 100 Standard LVDS R1a = R1b = R1 R2a = R2b = R2 Figure 3 L1 HCSL Output Buffer L1' R1a R1b L2 R3 L2' R2a R2b L4 L4' L3' L3 R4 Down Device REF_CLK Input Cable Connected AC Coupled Application (figure 4) Component Value Note R5a, R5b 8.2K 5% R6a, R6b 1K 5% Cc 0.1 µF Vcm 0.350 volts Figure 4 3.3 Volts Cc Cc R5a R5b L4 L4' R6a R6b PCIe Device REF_CLK Input IDT® 19 Output Differential Buffer for PCIe Gen2 and QPI 11 1607C—04/19/11 11 Page

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