9DB106 Datasheet PDF - IDT
Part Number | 9DB106 | |
Description | Six Output Differential Buffer | |
Manufacturers | IDT | |
Logo | ||
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DATASHEET
9DB106
Description
Features/Benefits
The 9DB106 zero-delay buffer supports PCIe Gen1 and Gen2
clocking requirements. The 9DB106 is driven by a differential SRC
output pair from an IDT CK410/CK505-compliant main clock
generator. It attenuates jitter on the input clock and has a selectable
PLL bandwidth to maximize performance in systems with or without
Spread-Spectrum clocking. An SMBus interface allows control of
the PLL bandwidth and bypass options, while 2 clock request
(CLKREQ#) pins make the 9DB106 suitable for Express Card
applications.
•
•
•
•
•
CLKREQ# pin for outputs 1 and 4/ supports Express Card
applications
PLL or bypass mode/PLL can dejitter incoming clock
Selectable PLL bandwidth/minimizes jitter peaking in
downstream PLL's
Spread Spectrum Compatible/tracks spreading input clock
for low EMI
SMBus Interface/unused outputs can be disabled
Recommended Applications
6 Output Differential Buffer for PCIe Gen 2
Output Features
• 6 - 0.7V current mode differential output pairs (HCSL)
Key Specifications
• Cycle-to-cycle jitter < 50ps
• Output-to-output skew < 50 ps
Functional Block Diagram
CLKREQ1#
CLKREQ4#
CLK_INT
C LK_INC
PLL_BW
SMBDAT
SMBCLK
SPREAD
COMPATIBLE
PLL
CONTROL
LOGIC
PCIEX1
PCIEX4
PCIEX(0,2,3,5)
IREF
IDT® Six Output Differential Buffer for PCIe Gen 2
1
9DB106 REV K 04/20/11
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9DB106
Six Output Differential Buffer for PCIe Gen 2
Electrical Characteristics - Clock Input Parameters
TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
Input High Voltage -
DIF_IN
Input Low Voltage -
DIF_IN
Input Common Mode
Voltage - DIF_IN
VIHDIF
VILDIF
VCOM
Differential inputs
(single-ended measurement)
Differential inputs
(single-ended measurement)
Common Mode Input Voltage
MIN
600
VSS - 300
300
Input Amplitude - DIF_IN VSWING
Peak to Peak value
300
Input Slew Rate - DIF_IN dv/dt
Measured differentially
0.4
Input Leakage Current
IIN
VIN = VDD , VIN = GND
-5
Input Duty Cycle
dtin
Measurement from differential
wavefrom
45
Input Jitter - Cycle to
Cycle
JDIFIn
Differential Measurement
0
1 Guaranteed by design and characterization, not 100% tested in production.
2Slew rate measured through +/-75mV window centered around differential zero
TYP
800
0
MAX
1150
UNITS NOTES
mV 1
300 mV 1
1000 mV 1
1450 mV 1
8 V/ns 1,2
5 uA 1
55 % 1
125 ps 1
Electrical Characteristics - PLL Parameters
TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5%
Group
Parameter
Description
PLL Jitter Peaking jpeak-hibw
(PLL_BW = 1)
Min Typ Max Units Notes
0 1 2.5 dB
1,4
PLL Jitter Peaking jpeak-lobw
(PLL_BW = 0)
0 1 2 dB
PLL Bandwidth
pllHIBW
(PLL_BW = 1)
PLL Bandwidth
pllLOBW
(PLL_BW = 0)
PCIe Gen 1 phase jitter
(1.5 - 22 MHz)
PCIe Gen 2 jitter
(8-16 MHz, 5-16 MHz) Hi-Band >1.5MHz
Jitter, Phase
tjphasePLL
(PLL_BW=1)
PCIe Gen 2 jitter
(8-16 MHz, 5-16 MHz) Hi-Band >1.5MHz
(PLL_BW=0)
PCIe Gen 2 jitter
(8-16 MHz, 5-16 MHz) Lo-Band <1.5MHz
NOTES:
1. Guaranteed by design and characterization, not 100% tested in production.
2. See http://www.pcisig.com for complete specs
2 2.5
0.4 0.5
3 MHz
1 MHz
40 108 ps
2.7 3.1 ps rms
2.2 3.1 ps rms
1.3 3 ps rms
3. Device driven by 932S421BGLF or equivalent
4. Measured as maximum pass band gain. At frequencies w ithin the loop BW, highest point of magnification is called PLL jitter peaking.
5. Measured at 3 db dow n or half pow er point.
1,4
1,5
1,5
1,2,3
1,2,3
1,2,3
1,2,3
IDT® Six Output Differential Buffer for PCIe Gen 2
9DB106 REV K 04/20/11
5
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Information | Total 14 Pages | |
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