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Número de pieza | ICS9DB102 | |
Descripción | Two Output Differential Buffer | |
Fabricantes | IDT | |
Logotipo | ||
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No Preview Available ! Two Output Differential Buffer for PCIe Gen1 & Gen2
DATASHEET
ICS9DB102
Description
The ICS9DB102 zero-delay buffer supports PCI Express
clocking requirements. The ICS9DB102 is driven by a differential
SRC output pair from an ICS CK410/CK505-compliant main
clock. It attenuates jitter on the input clock and has a selectable
PLL Band Width to maximize performance in systems with or
without Spread-Spectrum clocking.
Output Features
• 2 - 0.7V current mode differential output pairs (HCSL)
Features/Benefits
• CLKREQ# pin for outputs 1 and 4/output enable for Express
Card applications
• PLL or bypass mode/PLL can dejitter incoming clock
• Selectable PLL bandwidth/minimizes jitter peaking in
downstream PLL’s
• Spread Spectrum Compatible/tracks spreading input clock
for low EMI
• SMBus Interface/unused outputs can be disabled
• Industrial temperature range available
Key Specifications
• Cycle-to-cycle jitter < 35ps
• Output-to-output skew < 25ps
Functional Block Diagram
CLKREQ0#
CLKREQ1#
CLK_INT
C LK_IN C
PLL_BW
SMBDAT
SMBCLK
SPREAD
COMPATIBLE
PLL
CONTROL
LOGIC
PCIEX0
PCIEX1
IREF
IDT® Two Output Differential Buffer for PCIe Gen1 & Gen2
1
852 REV K 04/01/10
1 page ICS9DB102
Two Output Differential Buffer for PCIe Gen1 & Gen2
Electrical Characteristics - PLL Parameters
TA = Tambient; Supply Voltage VDD = 3.3 V +/-5%
Group
Parameter
Description
PLL Jitter Peaking jpeak-hibw
(PLL_BW = 1)
Min Typ Max Units Notes
0 1 2.5 dB 1,4
PLL Jitter Peaking jpeak-lobw
(PLL_BW = 0)
0 1 2 dB 1,4
PLL Bandwidth
pllHIBW
(PLL_BW = 1)
PLL Bandwidth
pllLOBW
(PLL_BW = 0)
PCIe Gen 1 phase jitter
(1.5 - 22 MHz)
PCIe Gen 2 jitter
(8-16 MHz, 5-16 MHz) Hi-Band >1.5MHz
Jitter, Phase
tjphasePLL
(PLL_BW=1)
PCIe Gen 2 jitter
(8-16 MHz, 5-16 MHz) Hi-Band >1.5MHz
(PLL_BW=0)
PCIe Gen 2 jitter
(8-16 MHz, 5-16 MHz) Lo-Band <1.5MHz
NOTES:
1. Guaranteed by design and characterization, not 100% tested in production.
2. See http://www.pcisig.com for complete specs
2 2.5
0.4 0.5
3 MHz
1 MHz
40 108 ps
1,5
1,5
1,2,3
2.7 3.1 ps rms 1,2,3
2.2 3.1 ps rms 1,2,3
1.3 3 ps rms 1,2,3
3. Device driven by 932S421BGLF or equivalent
4. Measured as maximum pass band gain. At frequencies w ithin the loop BW, highest point of magnification is called PLL jitter peaking.
5. Measured at 3 db dow n or half pow er point.
IDT® Two Output Differential Buffer for PCIe Gen1 & Gen2
5
852 REV K 04/01/10
5 Page ICS9DB102
Two Output Differential Buffer for PCIe Gen1 & Gen2
20-Pin SSOP Package Drawing and Dimensions
SYMBOL
A
A1
A2
b
c
D
E
E1
e
L
N
a
ZD
20-Lead, 150 mil SSOP (QSOP)
In Millimeters
In Inches
COMMON DIMENSIONS COMMON DIMENSIONS
MIN MAX MIN MAX
1.35
1.75 .053
.069
0.10
0.25 .004
.010
-- 1.50 -- .059
0.20
0.30 .008
.012
0.18
0.25 .007
.010
SEE VARIATIONS
SEE VARIATIONS
5.80
6.20 .228
.244
3.80
4.00 .150
.157
0.635 BASIC
0.025 BASIC
0.40
1.27 .016
.050
SEE VARIATIONS
SEE VARIATIONS
0° 8° 0° 8°
SEE VARIATIONS
SEE VARIATIONS
IDT® Two Output Differential Buffer for PCIe Gen1 & Gen2
11
852 REV K 04/01/10
11 Page |
Páginas | Total 13 Páginas | |
PDF Descargar | [ Datasheet ICS9DB102.PDF ] |
Número de pieza | Descripción | Fabricantes |
ICS9DB102 | Two Output Differential Buffer | IDT |
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