DataSheet.es    


PDF 9FGV0641 Data sheet ( Hoja de datos )

Número de pieza 9FGV0641
Descripción 6-O/P 1.8V PCIe Gen 1-2-3 Clock Generator
Fabricantes IDT 
Logotipo IDT Logotipo



Hay una vista previa y un enlace de descarga de 9FGV0641 (archivo pdf) en la parte inferior de esta página.


Total 15 Páginas

No Preview Available ! 9FGV0641 Hoja de datos, Descripción, Manual

6-O/P 1.8V PCIe Gen 1-2-3 Clock Generator
w/Zo=100ohms
9FGV0641
DATASHEET
General Description
The 9FGV0641 is a member of IDT's SOC-Friendly 1.8V
Very-Low-Power PCIe clock family. The device has integrated
100 ohm output terminations providing direction connection to
100 ohm transmission lines. The device also has 6 output
enables for clock management and supports 2 different
spread spectrum levels in addition to spread off.
Recommended Application
1.8V PCIe Gen 1-2-3 Clock Generator
Output Features
6 - 100MHz Low-Power (LP) HCSL DIF pairs w/Zo=100
1 - 1.8V LVCMOS REF output w/Wake-On-LAN (WOL)
support
Key Specifications
DIF cycle-to-cycle jitter <50ps
DIF output-to-output skew <50ps
DIF phase jitter is PCIe Gen1-2-3 compliant
REF phase jitter is <1.5ps RMS
Block Diagram
Features/Benefits
LP-HCSL outputs with integrated terminations; save 24
resistors compared to standard PCIe devices
54mW typical power consumption; reduced thermal
concerns
Outputs can optionally be supplied from any voltage
between 1.05V and 1.8V; maximum power savings
OE# pins; support DIF power management
Programmable Slew rate for each output; allows tuning for
various line lengths
Programmable output amplitude; allows tuning for various
application environments
DIF outputs blocked until PLL is locked; clean system
start-up
Selectable 0%, -0.25% or -0.5% spread on DIF outputs;
reduces EMI
External 25MHz crystal; supports tight ppm with 0 ppm
synthesis error
Configuration can be accomplished with strapping pins;
SMBus interface not required for device control
3.3V tolerant SMBus interface works with legacy controllers
Selectable SMBus addresses; multiple devices can easily
share an SMBus segment
Space saving 40-pin 5x5 mm VFQFPN; minimal board
space
vOE(5:0)#
XIN/CLKIN_25
X2
6
OSC
vSADR
vSS_EN_tri
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
CONTROL
LOGIC
SS Capable PLL
REF1.8
DIF5
DIF4
DIF3
DIF2
DIF1
DIF0
9FGV0641 OCTOBER 18, 2016
1 ©2016 Integrated Device Technology, Inc.

1 page




9FGV0641 pdf
9FGV0641 DATASHEET
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 9FGV0641. These ratings, which are standard
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the
recommended operating temperature range.
PARAMETER
SYMBOL
CONDITIONS
Supply Voltage
VDDxx
Applies to all VDD pins
Input Voltage
VIN
Input High Voltage, SMBus VIHSMB
Storage Temperature
Ts
SMBus clock and data pins
Junction Temperature
Tj
Input ESD protection ESD prot
Human Body Model
1Guaranteed by design and characterization, not 100% tested in production.
2 Operation under these conditions is neither implied nor guaranteed.
3 Not to exceed 2.5V.
MIN
-0.5
-0.5
-65
2000
TYP
MAX
2.5
VDD+0.5V
3.6V
150
125
UNITS
V
V
V
°C
°C
V
NOTES
1,2
1, 3
1
1
1
1
Electrical Characteristics–Current Consumption
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS NOTES
Operating Supply Current
IDDAOP
IDDOP
VDDA, All outputs active @100MHz
All VDD, except VDDA and VDDIO, All outputs
active @100MHz
6.2 9
10.2 15
mA
mA
IDDIOOP
VDDIO, All outputs active @100MHz
23
Wake-on-LAN Current
(CKPWRGD_PD# = '0'
Byte 3, bit 5 = '1')
IDDAPD
IDDPD
IDDIOPD
VDDA, DIF outputs off, REF output running
All VDD, except VDDA and VDDIO,
DIF outputs off, REF output running
VDDIO, DIF outputs off, REF output running
0.4
5.3
0.04
Powerdown Current
IDDAPD
VDDA, all outputs off
0.4
(CKPWRGD_PD# = '0'
Byte 3, bit 5 = '0')
IDDPD All VDD, except VDDA and VDDIO, all outputs off
IDDIOPD
VDDIO, all outputs off
0.6
0.0005
1 Guaranteed by design and characterization, not 100% tested in production.
2 This is the current required to have the REF output running in Wake-on-LAN mode (Byte 3, bit 5 = 1)
30
1
8
0.1
1
1
0.1
mA
mA
mA
mA
mA
mA
mA
2
2
2
Electrical Characteristics–DIF Output Duty Cycle, Jitter, and Skew Characteristics
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS NOTES
Duty Cycle
tDC Measured differentially, PLL Mode
Skew, Output to Output
tsk3
Averaging on, VT = 50%
Jitter, Cycle to cycle
tjcyc-cyc
1Guaranteed by design and characterization, not 100% tested in production.
2 Measured from differential waveform
45 50 55 % 1,2
43 50 ps 1,2
14 50 ps 1,2
OCTOBER 18, 2016
5 6-O/P 1.8V PCIE GEN 1-2-3 CLOCK GENERATOR W/ZO=100OHMS

5 Page





9FGV0641 arduino
9FGV0641 DATASHEET
SMBus Table: Revision and Vendor ID Register
Byte 5
Name
Control Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RID3
RID2
RID1
RID0
VID3
VID2
VID1
VID0
Revision ID
VENDOR ID
Type
R
R
R
R
R
R
R
R
01
C rev = 0001
0001 = IDT
Default
0
0
0
1
0
0
0
1
SMBus Table: Device Type/Device ID
Byte 6
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Device Type1
Device Type0
Device ID5
Device ID4
Device ID3
Device ID2
Device ID1
Device ID0
Control Function
Device Type
Device ID
Type
R
R
R
R
R
R
R
R
01
00 = FGx, 01 = DBx ZDB/FOB,
10 = DMx, 11= DBx FOB
000110 binary or 06 hex
Default
0
0
0
0
0
1
1
0
SMBus Table: Byte Count Register
Byte 7
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BC4
BC3
BC2
BC1
BC0
Control Function
Reserved
Reserved
Reserved
Byte Count Programming
Type
0
1
RW
RW Writing to this register will configure how
RW many bytes will be read back, default is
RW = 8 bytes.
RW
Default
0
0
0
0
1
0
0
0
Recommended Crystal Characteristics (3225 package)
PARAMETER
Frequency
Resonance Mode
Frequency Tolerance @ 25°C
Frequency Stability, ref @ 25°C Over
Operating Temperature Range
Temperature Range (commerical)
Temperature Range (industrial)
Equivalent Series Resistance (ESR)
Shunt Capacitance (CO)
Load Capacitance (CL)
Drive Level
Aging per year
Notes:
1. FOX 603-25-150.
2. For I-temp, FOX 603-25-261.
VALUE
25
Fundamental
±20
±20
0~70
-40~85
50
7
8
0.3
±5
UNITS
MHz
-
PPM Max
NOTES
1
1
1
PPM Max
°C
°C
Max
pF Max
pF Max
mW Max
PPM Max
1
1
2
1
1
1
1
1
OCTOBER 18, 2016
11 6-O/P 1.8V PCIE GEN 1-2-3 CLOCK GENERATOR W/ZO=100OHMS

11 Page







PáginasTotal 15 Páginas
PDF Descargar[ Datasheet 9FGV0641.PDF ]




Hoja de datos destacado

Número de piezaDescripciónFabricantes
9FGV06416-O/P 1.8V PCIe Gen 1-2-3 Clock GeneratorIDT
IDT

Número de piezaDescripciónFabricantes
SLA6805M

High Voltage 3 phase Motor Driver IC.

Sanken
Sanken
SDC1742

12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.

Analog Devices
Analog Devices


DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.


DataSheet.es    |   2020   |  Privacy Policy  |  Contacto  |  Buscar